CN-116258117-B - Chip simulation verification system and method

CN116258117BCN 116258117 BCN116258117 BCN 116258117BCN-116258117-B

Abstract

The embodiment of the application provides a chip simulation verification system and a chip simulation verification method, wherein the chip simulation verification system comprises a front-end server, a hardware simulation accelerator and at least one interface expander, wherein the front-end server is provided with at least one first interface, the first interface is connected with a second interface on one interface expander, each interface expander comprises a second interface and at least two third interfaces connected with the second interface, the hardware simulation accelerator comprises at least two simulation units, each simulation unit is connected with one third interface, different simulation units are connected with different third interfaces, the simulation units are used for simulating a chip to be verified, and the front-end server is used for communicating with each simulation unit through the interface expander respectively and verifying the chip to be verified simulated by the simulation units. The scheme can improve the applicability of chip simulation verification.

Inventors

WANG CHAOJIE
ZHANG TIANFANG
WANG YIZHOU
XIAO DEYU

Assignees

平头哥(上海)半导体技术有限公司

Dates

Publication Date: 20260512
Application Date: 20220824

Claims (9)

1. A chip simulation verification system comprises a front-end server, a hardware simulation accelerator and at least one interface expander; The front-end server is provided with at least one first interface, the first interface is configured to be connected with a second interface on one interface expander, and each interface expander comprises one second interface and at least two third interfaces connected with the second interface; the hardware simulation accelerator comprises at least two simulation units, each simulation unit is connected with one third interface, and different simulation units are connected with different third interfaces; the simulation unit is used for simulating the chip to be verified; The front-end server is used for communicating with each simulation unit through the interface expander respectively and verifying the chip to be verified simulated by each simulation unit; the chip simulation verification system also comprises at least two rate conversion units; each third interface is connected with one speed conversion unit, and different third interfaces are connected with different speed conversion units; said transrating unit being configured to be coupled to one of said analog units, different ones of said transrating units being coupled to different ones of said analog units; The rate conversion unit is used for caching communication data between the connected analog unit and the front-end server.
2. The chip emulation verification system of claim 1 wherein the interface extender comprises an extender plate, at least one connector plate, and at least two connector wires; The expansion board is provided with one second interface and at least two first connecting line interfaces connected with the second interface; at least one second connecting wire interface and at least one third interface are arranged on the connecting plate, and different second connecting wire interfaces are connected with different third interfaces; Each first connecting wire interface is connected with one second connecting wire interface through one connecting wire, and different first connecting wire interfaces are connected with different second connecting wire interfaces.
3. The chip simulation verification system according to claim 2, wherein at least two second connection line interfaces and at least two third interfaces are provided on each connection board, and different second connection line interfaces are connected with different third interfaces.
4. The chip emulation verification system of claim 2 wherein the number of first connection line interfaces on each expansion board is n, the bandwidth of each first connection line interface being equal to 1/n of the bandwidth of the second interface.
5. The chip emulation verification system of claim 2 wherein the first interface, the second interface and the third interface are all high-speed serial computer expansion bus standard interfaces.
6. The chip emulation verification system of claim 5 wherein the first connection wire interface and the second connection wire interface are both Mini SAS interfaces and the connection wire is a Mini SAS connection wire.
7. The chip emulation verification system of any one of claims 1 to 6 wherein the parallel processing units emulated by each of the emulation units are connected to an inter-chip communication unit; the inter-chip communication unit simulated by each simulation unit is connected with the inter-chip communication unit simulated by at least one other simulation unit; the parallel processing unit is used for executing the parallel processing task sent by the front-end server; the inter-chip communication unit is used for transmitting communication data between the connected parallel processing units.
8. The chip emulation verification system of claim 7 wherein the analog unit comprises a format conversion unit; The format conversion unit is connected with an interface IP core which is simulated by the simulation unit, and the interface IP core is connected with the parallel processing unit; the format conversion unit is configured to be connected to one of the rate conversion units, and perform format conversion on data transmitted between the connected rate conversion unit and the interface IP core.
9. A chip emulation verification method comprising: The hardware simulation accelerator comprises at least two simulation units for simulating at least two chips to be verified; the front-end server is respectively communicated with each analog unit through an interface expander to verify chips to be verified, which are simulated by the analog units, wherein at least one first interface is arranged on the front-end server and is configured to be connected with a second interface on one interface expander, each interface expander comprises one second interface and at least two third interfaces connected with the second interface, each third interface is connected with one rate conversion unit, different third interfaces are connected with different rate conversion units, each rate conversion unit is connected with one analog unit, different rate conversion units are connected with different analog units, and the rate conversion units are used for caching communication data between the connected analog units and the front-end server.

Description

Chip simulation verification system and method Technical Field The embodiment of the application relates to the technical field of chips, in particular to a chip simulation verification system and method. Background In the design development process of the chip, the hardware code of the chip is simulated and verified through the hardware simulation accelerator, so that the accuracy of circuit design in the chip can be verified in advance, the hardware code of the chip is iterated based on a verification result, and the design development efficiency of the chip is improved. When simulation verification is performed on some chips, it is required to verify whether the operation condition of the interconnected chips meets the design requirement, for example, verify whether the data bandwidth of the interconnected 8 chips matches the architecture design. When simulation verification is performed on the multi-chip interconnection, the hardware simulation accelerator simulates a plurality of chips, and the front-end server controls the hardware simulation accelerator to verify the chip interconnection function. Currently, when performing simulation verification on multi-chip interconnection, a front-end server with a corresponding number of interfaces needs to be selected according to the number of interconnection chips, so that each chip simulated by a hardware simulation accelerator is connected with the front-end server through one interface. However, when performing simulation verification of different numbers of chip interconnections with respect to the same chip, for example, when performing simulation verification of 2/4/8 chip interconnections with respect to the same chip, the number of interconnected chips may exceed the upper limit of the interface of the front-end server, for example, the front-end server includes 4 interfaces that can be connected to the hardware simulation accelerator, and then chip interconnection simulation verification of less than or equal to 4 interconnected chips may be performed through the front-end server, and 8 chip interconnection simulation verification may not be performed through the front-end server, so the applicability of the chip simulation verification system is poor. Disclosure of Invention In view of the above, embodiments of the present application provide a system and a method for chip simulation verification to at least solve or alleviate the above-mentioned problems. According to a first aspect of the embodiment of the application, a chip simulation verification system is provided, which comprises a front-end server, a hardware simulation accelerator and at least one interface expander, wherein at least one first interface is arranged on the front-end server and is configured to be connected with a second interface on one interface expander, each interface expander comprises one second interface and at least two third interfaces connected with the second interfaces, the hardware simulation accelerator comprises at least two simulation units, each simulation unit is connected with one third interface, different simulation units are connected with different third interfaces, the simulation units are used for simulating chips to be verified, and the front-end server is used for respectively communicating with each simulation unit through the interface expander and verifying the chips to be verified, which are simulated by the simulation units. According to a second aspect of the embodiment of the application, a chip simulation verification method is provided, which comprises the steps that at least two simulation units included in a hardware simulation accelerator simulate at least two chips to be verified, a front-end server is respectively communicated with each simulation unit through an interface expander and verifies the chips to be verified simulated by each simulation unit, at least one first interface is arranged on the front-end server and is configured to be connected with a second interface on one interface expander, each interface expander comprises one second interface and at least two third interfaces connected with the second interfaces, each simulation unit is connected with one third interface, and different simulation units are connected with different third interfaces. According to the chip simulation verification scheme provided by the embodiment of the application, the front-end server comprises at least one first interface, each first interface can be connected with a second interface on one interface expander, a plurality of third interfaces are arranged on each interface expander, each third interface can be connected with one simulation unit included in the hardware simulation accelerator, each simulation unit can simulate a chip to be verified, and the front-end server is respectively communicated with each simulation unit through the interface expander so as to verify the chip to be verified simulated by each simulation unit. The inter