CN-116259349-B - Antifuse circuit for sensing antifuse

Abstract

An antifuse circuit includes a current generator and an antifuse sensing unit. The current generator has at least one replica electronic component. The anti-fuse sensing unit is electrically connected with the current generator and is provided with at least one electronic element. The electronic component specification of at least one electronic component of the antifuse sensing unit is the same as the electronic component specification of at least one replica electronic component of the current generator. The current generator supplies current to the antifuse sensing unit to sense the antifuse. By the technical scheme of the invention, the anti-fuse circuit can improve the accuracy of sensing the anti-fuse.

Inventors

• CHEN ZHIREN

Assignees

• 南亚科技股份有限公司

Dates

Publication Date

20260508

Application Date

20220121

Priority Date

20211212

Claims (13)

1. 1. An antifuse circuit, comprising: a current generator having at least one replica electronic component, and An antifuse sensing unit electrically connected to the current generator, the antifuse sensing unit having at least one electronic device, The anti-fuse sensing unit comprises an inverter, the inverter comprises a first P-type metal oxide semiconductor (PMOS) transistor and a first N-type metal oxide semiconductor (NMOS) transistor, the current generator comprises a voltage divider, the voltage divider comprises a first P-type metal oxide semiconductor transistor, a first resistor, a second resistor and a first N-type metal oxide semiconductor transistor which are connected in series, the at least one electronic element of the anti-fuse sensing unit comprises the first P-type metal oxide semiconductor transistor and the first N-type metal oxide semiconductor transistor of the inverter, the at least one electronic element of the current generator comprises the first P-type metal oxide semiconductor transistor and the first N-type metal oxide semiconductor transistor of the voltage divider, the electronic element specification of the first P-type metal oxide semiconductor transistor is identical to the electronic element of the first P-type metal oxide semiconductor transistor, the electronic element specification of the first N-type metal oxide semiconductor transistor is identical to the electronic element specification of the first P-type metal oxide semiconductor transistor, and the current sensing unit is supplied with the current.
2. 2. The antifuse circuit of claim 1, wherein a source of the first pmos is electrically coupled to an operating voltage, a source of the first nmos is electrically coupled to a ground voltage, a gate of the first nmos is electrically connected to the gate of the first pmos, a drain of the first nmos is electrically connected to the drain of the first pmos, a drain of the first pmos is directly connected to the gate of the first pmos, and a drain of the first pmos is directly connected to the gate of the first pmos.
3. 3. The antifuse circuit of claim 1, wherein the antifuse sensing unit further comprises: the second PMOS transistor is provided with a grid electrode, a source electrode and a drain electrode, wherein the source electrode of the second PMOS transistor is electrically coupled with the working voltage, and the drain electrode of the second PMOS transistor is electrically connected with the grid electrode of the first PMOS transistor and the grid electrode of the first NMOS transistor; one end of the antifuse is electrically connected to the drain of the second pmos transistor, and the other end of the antifuse is electrically coupled to a ground voltage.
4. 4. The antifuse circuit of claim 3, wherein the current generator further comprises: A current source electrically coupled to the ground voltage in proportion to absolute temperature, and The complementary absolute temperature resistor is electrically coupled to the ground voltage, wherein the proportional absolute temperature current source and the complementary absolute temperature resistor are connected in parallel to simulate the electrical characteristics of the antifuse.
5. 5. The antifuse circuit of claim 4, wherein the current generator further comprises: the operational amplifier is provided with a non-inverting input end, an inverting input end and an output end, wherein the non-inverting input end is electrically connected between the first resistor and the second resistor of the voltage divider, and the inverting input end is electrically connected with the proportional absolute temperature current source and the complementary absolute temperature resistor; A third PMOS transistor having a gate, a source and a drain, wherein the gate of the third PMOS transistor is electrically connected to the output terminal of the operational amplifier, the source of the third PMOS transistor is electrically coupled to the operating voltage, the drain of the third PMOS transistor is electrically connected to the inverting input terminal of the operational amplifier, and The second replica pmos transistor has a gate, a source and a drain, the gate of the second replica pmos transistor is electrically connected to the output terminal of the operational amplifier, the source of the second replica pmos transistor is electrically coupled to the operating voltage, the drain of the second replica pmos transistor is electrically connected to the antifuse sensing unit, wherein the at least one electronic component of the antifuse sensing unit further comprises the second pmos transistor, the at least one replica electronic component of the current generator further comprises the second replica pmos transistor, and the electronic component specification of the second replica pmos transistor is the same as the electronic component specification of the second pmos transistor.
6. 6. The antifuse circuit of claim 5, wherein the antifuse sensing unit further comprises a current mirror comprising: A fourth pmos transistor having a gate, a source, and a drain, the source of the fourth pmos transistor being electrically coupled to the operating voltage, the drain of the fourth pmos transistor being electrically connected to the gate of the second pmos transistor and the gate of the fourth pmos transistor; A second NMOS transistor having a gate, a source and a drain, the gate of the second NMOS transistor electrically connected to the drain of the second replica PMOS transistor, the source of the second NMOS transistor electrically coupled to the ground voltage, the drain of the second NMOS transistor electrically connected to the drain of the fourth PMOS transistor, and The third NMOS transistor has a gate, a source and a drain, the gate of the third NMOS transistor is electrically connected to the drain of the second PMOS transistor, the source of the third NMOS transistor is electrically coupled to the ground voltage, and the drain of the third NMOS transistor is electrically connected to the gate of the third NMOS transistor, the gate of the second NMOS transistor and the drain of the second PMOS transistor.
7. 7. An antifuse circuit, comprising: A current generator for dividing the voltage by a voltage divider to provide a divided voltage and generating a current by the voltage to the current unit according to the divided voltage and the analog voltage, and An antifuse sensing unit electrically coupled to the current generator for receiving the current, sensing the antifuse according to the current to generate a sensing result, and outputting the sensing result through an inverter; Wherein the channel length, channel width, and threshold voltage of the transistors in the voltage divider are the same as the channel length, channel width, and threshold voltage of the transistors in the inverter.
8. 8. The antifuse circuit of claim 7, wherein the voltage-to-current cell comprises a proportional-to-absolute-temperature current source in parallel with a complementary-to-absolute-temperature resistor to provide the analog voltage.
9. 9. The antifuse circuit of claim 8, wherein the voltage-to-current cell comprises: an operational amplifier for receiving the divided voltage and the analog voltage, and And the output transistor is electrically coupled to the operational amplifier, wherein the output transistor is controlled by the operational amplifier to output the current.
10. 10. The antifuse circuit of claim 9, wherein the antifuse sensing unit comprises a sense transistor electrically coupled to the antifuse to sense the antifuse based on the current from the current generator.
11. 11. The antifuse circuit of claim 10, wherein the antifuse sensing unit comprises a current mirror electrically coupled to the output transistor and the sense transistor, wherein the current mirror receives the current to control the sense transistor.
12. 12. The antifuse circuit of claim 10, wherein a channel length, a channel width, and a threshold voltage of the output transistor are the same as a channel length, a channel width, and a threshold voltage of the sense transistor.
13. 13. The antifuse circuit of claim 12, wherein the output transistor and the sense transistor are P-type transistors.

Description

Antifuse circuit for sensing antifuse Technical Field The present invention relates to a device, and more particularly to a device for sensing an antifuse in a dynamic random access memory. Background Currently, dynamic Random Access Memory (DRAM) employs antifuse technology. An antifuse is an electrical device whose characteristics are opposite to those of a fuse. In a DRAM, antifuses can be programmed to determine redundant rows and redundant columns. Taking antifuse as an example, blown antifuse has low resistance and unblown antifuse has high resistance. If the high resistance or low resistance of the antifuse is judged to be wrong, the wrong redundant rows and columns are judged, thereby adversely affecting the yield of the DRAM. Disclosure of Invention The present invention provides an antifuse circuit that ameliorates the problems of the prior art. In an embodiment of the present invention, an antifuse circuit includes a current generator and an antifuse sensing unit. The current generator has at least one replica electronic component. The anti-fuse sensing unit is electrically connected with the current generator and is provided with at least one electronic element. The electronic component specification of at least one electronic component of the antifuse sensing unit is the same as the electronic component specification of at least one replica electronic component of the current generator. The current generator supplies current to the antifuse sensing unit to sense the antifuse. In an embodiment of the invention, the antifuse sensing unit includes an inverter including a first PMOS transistor and a first NMOS transistor, the current generator includes a voltage divider including a first PMOS transistor, a first resistor, a second resistor, and a first NMOS transistor connected in series, at least one electronic element of the antifuse sensing unit includes the first PMOS transistor and the first NMOS transistor of the inverter, at least one replica electronic element of the current generator includes the first PMOS transistor and the first NMOS transistor of the voltage divider, the electronic element of the first PMOS transistor is identical to the electronic element of the first PMOS transistor, and the electronic element of the first PMOS transistor is identical to the electronic element of the first NMOS transistor. In an embodiment of the present invention, a source of the first pmos is electrically coupled to the operating voltage, a source of the first nmos is electrically coupled to the ground voltage, a gate of the first nmos is electrically connected to the gate of the first pmos, a drain of the first nmos is electrically connected to the drain of the first pmos, a drain of the first pmos is directly connected to the gate of the first pmos, and a drain of the first pmos is directly connected to the gate of the first nmos. In an embodiment of the invention, the antifuse sensing unit further comprises a second pmos transistor. The second PMOS transistor has a gate, a source and a drain, the source of the second PMOS transistor is electrically coupled to the operating voltage, and the drain of the second PMOS transistor is electrically connected to the gate of the first PMOS transistor and the gate of the first NMOS transistor. One end of the antifuse is electrically connected to the drain of the second pmos transistor, and the other end of the antifuse is electrically coupled to the ground voltage. In one embodiment of the present invention, the current generator further comprises a proportional to absolute temperature (proportional to absolute temperature) current source and a complementary to absolute temperature (complementary to absolute temperature) resistor. The proportional to absolute temperature current source is electrically coupled to the ground voltage, the complementary to absolute temperature resistor is electrically coupled to the ground voltage, the proportional to absolute temperature current source is parallel to the complementary to absolute temperature resistor to simulate the electrical characteristics of an antifuse. In an embodiment of the invention, the current generator further includes an operational amplifier, a third pmos transistor, and a second replica pmos transistor. The operational amplifier has a non-inverting input end, an inverting input end and an output end, wherein the non-inverting input end is electrically connected between the first resistor and the second resistor of the voltage divider, and the inverting input end is electrically connected with the proportional absolute temperature current source and the complementary absolute temperature resistor. The third P-type metal oxide semiconductor transistor is provided with a grid electrode, a source electrode and a drain electrode, wherein the grid electrode of the third P-type metal oxide semiconductor transistor is electrically connected with the output end of the operational amplifier, the source e