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CN-116260332-B - Method and system for setting size of power switch transistor

CN116260332BCN 116260332 BCN116260332 BCN 116260332BCN-116260332-B

Abstract

The invention provides a size setting method of a power switch transistor. The first load current acquisition step acquires a first load current of the first logic circuit. The second load current obtaining step obtains a second load current of the second logic circuit. The limiting voltage drop calculating step calculates a limiting voltage drop according to the speed ratio value, the first load current and the second load current. The reference supply current calculating step calculates the reference supply current from the limit voltage drop. The analog supply current calculating step calculates an analog supply current based on the reference supply current, the limit voltage drop, and the line voltage value. The size setting step compares the first load current with the analog supply current to calculate a size parameter, and sets the size of the power switch transistor according to the size parameter. Thereby, a high reaction speed of the logic circuit is maintained.

Inventors

  • Jian Shunrong

Assignees

  • 美商矽成积体电路股份有限公司

Dates

Publication Date
20260505
Application Date
20211209

Claims (12)

  1. 1. A method for sizing a power switching transistor, comprising the steps of: A first load current obtaining step, driving an operation processing unit to obtain a first load current of a first logic circuit, wherein the first logic circuit is connected to a power voltage through at least one power switch transistor and at least one power line to generate the first load current, and the at least one power line has at least one line voltage value; A second load current obtaining step, driving the operation processing unit to obtain a second load current of a second logic circuit, wherein the second logic circuit is connected to the power supply voltage to generate the second load current; A step of calculating a limiting voltage drop, in which the operation processing unit is driven to set a speed ratio value and store the speed ratio value into a storage unit, and the operation processing unit performs a voltage calculation procedure on the speed ratio value, the first load current and the second load current to calculate a limiting voltage drop between the at least one power switch transistor and the first logic circuit; A reference supply current calculating step of driving the operation processing unit to calculate a reference supply current of the at least one power switching transistor according to the limiting voltage drop; A step of calculating an analog supply current by driving the operation processing unit to perform a current calculation process on the reference supply current, the limiting voltage drop and the at least one line voltage value to calculate an analog supply current of the at least one power switching transistor, and A dimension setting step of driving the operation processing unit to compare the first load current with the analog supply current to calculate a dimension parameter, and then setting a dimension of the at least one power switch transistor according to the dimension parameter; Wherein the voltage calculation program comprises the speed ratio value, the first load current, the second load current, the power supply voltage, a threshold voltage and a terminal voltage between the at least one power supply line and the first logic circuit, the speed ratio value is represented as S, and the first load current is represented as The second load current is expressed as The supply voltage is expressed as The critical voltage is expressed as The terminal voltage is expressed as And conforms to the formula: The operation processing unit limits a difference value between the terminal voltage and the power supply voltage to be the limiting voltage drop according to the speed proportion value; wherein the current calculation program comprises the analog supply current, the reference supply current, the limiting voltage drop and the at least one line voltage value, the analog supply current being expressed as The reference supply current is expressed as The limiting voltage drop is expressed as The at least one line voltage value is expressed as And conforms to the formula:
  2. 2. The method of claim 1, wherein the first logic circuit has a structure identical to a structure of the second logic circuit.
  3. 3. The method of dimensioning a power switching transistor according to claim 1, wherein the first logic circuit comprises a plurality of transistors, and the first load current obtaining step comprises: The power supply voltage is connected to a first power domain and a second power domain of the first logic circuit through the at least one power switch transistor and the at least one power line, so that the transistors operate in a saturation region and generate the first load current.
  4. 4. The method of dimensioning a power switching transistor according to claim 1, wherein the second logic circuit comprises a plurality of transistors, and the second load current obtaining step comprises: And connecting another power supply voltage to a first power supply domain and a second power supply domain of the second logic circuit, so that the transistors operate in a saturation region and generate the second load current.
  5. 5. The method of sizing a power switching transistor according to claim 1, wherein the reference supply current calculating step comprises: a presetting sub-step for driving the operation processing unit to preset the limiting voltage drop to be a drain-source voltage of the at least one power switch transistor to make the at least one power switch transistor operate in a linear region, and An calculation sub-step, driving the operation processing unit to calculate the reference supply current according to the drain-source voltage.
  6. 6. The method of claim 1, wherein the at least one power switching transistor is a multiple threshold complementary metal oxide semiconductor.
  7. 7. A power switching transistor sizing system, comprising: A power supply voltage; at least one power switch transistor electrically connected to the power voltage; at least one power line electrically connected to the at least one power switch transistor and having at least one line voltage value; the first logic circuit is electrically connected with the at least one power line and generates a first load current; a second logic circuit electrically connected to the power supply voltage and generating a second load current; a memory unit for accessing the at least one line voltage value, a voltage calculation program and a current calculation program, and An arithmetic processing unit in signal connection with the memory unit, the arithmetic processing unit being configured to perform operations comprising: a first load current obtaining step of obtaining the first load current; a second load current obtaining step of obtaining the second load current; A limiting voltage drop calculating step, setting a speed ratio value and storing the speed ratio value into the memory unit, and then performing the voltage calculating procedure on the speed ratio value, the first load current and the second load current to calculate a limiting voltage drop between the at least one power switch transistor and the first logic circuit; A reference supply current calculating step of calculating a reference supply current of the at least one power switching transistor according to the limit voltage drop; an analog supply current calculating step of performing the current calculating process on the reference supply current, the limiting voltage drop and the at least one line voltage value to calculate an analog supply current of the at least one power switching transistor, and A dimension setting step of comparing the first load current with the analog supply current to calculate a dimension parameter, and then setting a dimension of the at least one power switch transistor according to the dimension parameter; Wherein the voltage calculation program comprises the speed ratio value, the first load current, the second load current, the power supply voltage, a threshold voltage and a terminal voltage between the at least one power supply line and the first logic circuit, the speed ratio value is represented as S, and the first load current is represented as The second load current is expressed as The supply voltage is expressed as The critical voltage is expressed as The terminal voltage is expressed as And conforms to the formula: The operation processing unit limits a difference value between the terminal voltage and the power supply voltage to be the limiting voltage drop according to the speed proportion value; wherein the current calculation program comprises the analog supply current, the reference supply current, the limiting voltage drop and the at least one line voltage value, the analog supply current being expressed as The reference supply current is expressed as The limiting voltage drop is expressed as The at least one line voltage value is expressed as And conforms to the formula:
  8. 8. the power switching transistor sizing system of claim 7, wherein the first logic circuit is configured identically to the second logic circuit.
  9. 9. The power switching transistor sizing system of claim 7, wherein the first logic circuit comprises a plurality of transistors, and the first load current acquisition step comprises: The at least one power switch transistor and the at least one power line are connected with the power voltage to a first power domain and a second power domain of the first logic circuit, so that the transistors operate in a saturation region and generate the first load current.
  10. 10. The power switching transistor sizing system according to claim 7, wherein the second logic circuit includes a plurality of transistors, and the second load current obtaining step includes: And connecting another power supply voltage to a first power supply domain and a second power supply domain of the second logic circuit, so that the transistors operate in a saturation region and generate the second load current.
  11. 11. The power switching transistor sizing system according to claim 7, wherein the reference supply current calculating step comprises: a presetting sub-step for driving the operation processing unit to preset the limiting voltage drop to be a drain-source voltage of the at least one power switch transistor to make the at least one power switch transistor operate in a linear region, and An calculation sub-step, driving the operation processing unit to calculate the reference supply current according to the drain-source voltage.
  12. 12. The power switch transistor size setting system according to claim 7, wherein the at least one power switch transistor is a multiple threshold voltage complementary metal oxide semiconductor.

Description

Method and system for setting size of power switch transistor Technical Field The present invention relates to a method and a system for setting the size of a power switch transistor, and more particularly, to a method and a system for setting the size of a power switch transistor by using a load current of a logic circuit, wherein the logic circuit configured with the power switch transistor still maintains high-speed transmission. Background In recent years, as electronic circuit devices incorporating semiconductor materials are increasingly increasing, there is an increasing demand for low power consumption technology, wherein a Multi-Threshold complementary metal oxide semiconductor (MTCMOS) is disposed in a logic circuit. MTCMOS is an effective power switch control technique that reduces leakage current and power consumption of logic circuits and maintains the desired speed performance of logic circuits by properly alternating high and low threshold voltage transistors. However, many MTCMOS as logic gates are often overloaded, greatly affecting the speed of the logic circuit. The main reason that the speed of an overloaded logic gate is slow is that the gate-source voltage (Vgs) becomes small due to the large voltage drop at the drain-source. An effective way to solve the foregoing is to configure the MTCMOS minimum size of the load (i.e., logic circuit) for the load. In view of this, how to build a method and system for setting the size of a power switch transistor capable of satisfying the speed required by a logic circuit is a great expectation for the public, and is a goal and direction for related industries to develop breakthrough. Disclosure of Invention It is therefore an object of the present invention to provide a size setting method of a power switching transistor and a system thereof, which calculate the size of the power switching transistor using a load current of a logic circuit and ensure that the logic circuit can maintain high-speed transmission. According to one embodiment of the present invention, a method for sizing a power switching transistor includes a first load current obtaining step, a second load current obtaining step, a voltage drop limiting calculating step, a reference supply current calculating step, an analog supply current calculating step, and a sizing step. The first load current obtaining step drives an operation processing unit to obtain a first load current of a first logic circuit. The first logic circuit is connected to a power voltage through at least one power switch transistor and at least one power line to generate a first load current, and the at least one power line has at least one line voltage value. The second load current obtaining step drives the operation processing unit to obtain a second load current of a second logic circuit. The second logic circuit is connected to the power supply voltage to generate a second load current. The voltage limiting step drives the operation processing unit to set a speed ratio value and stores the speed ratio value into a memory unit. The operation processing unit performs a voltage calculation procedure on the speed ratio value, the first load current and the second load current to calculate a limiting voltage drop between the at least one power switch transistor and the first logic circuit. The reference supply current calculating step drives the operation processing unit to calculate a reference supply current of the at least one power switch transistor according to the limiting voltage drop. The analog supply current calculating step drives the operation processing unit to perform a current calculating program on the reference supply current, the limiting voltage drop and the at least one line voltage value so as to calculate an analog supply current of the at least one power switch transistor. The size setting step drives the operation processing unit to compare the first load current with the analog supply current to calculate a size parameter, and then sets a size of the at least one power switch transistor according to the size parameter. The voltage calculation program comprises a speed proportion value, a first load current, a second load current, a power supply voltage, a critical voltage and a terminal voltage between the at least one power line and the first logic circuit. The speed ratio value is denoted as S, the first load current is denoted asThe second load current is expressed asThe supply voltage is expressed asThe critical voltage is expressed asThe terminal voltage is expressed asAnd conforms to the formula: in addition, the operation processing unit can limit the voltage drop according to a difference between the terminal voltage and the power voltage of the speed ratio value. The current calculation program comprises an analog supply current, a reference supply current, a limiting voltage drop and at least one line voltage value. The analog supply current is expressed asThe reference supply c