CN-116302015-B - Method for loading, solidifying and updating FPGA program realized by double soft cores

Abstract

The invention discloses a method for loading, solidifying and updating an FPGA program realized by double soft cores, which comprises the steps of simultaneously running MicroBlaze double soft cores in an FPGA, implementing double-thread operation, realizing network data transmission, storage and information interaction functions by utilizing MicroBlaze_0 soft core control, realizing file data reading by utilizing MicroBlaze_1 soft core control, and performing data writing, reading and rewriting functions on FLASH firmware. The invention can promote the speed of program loading, curing and updating through the network port and provide real-time program updating state information.

Inventors

• FAN QINGSHUAI
• Su Yangmuyu
• LIN YU
• DU XINYUE
• LIN DANDAN
• ZHU LIANG
• Zi Ruixiao
• LI WEI
• ZHANG JIN
• WANG YUANYU
• ZHANG QIANG
• YAN XINJIE
• SONG ZHIHANG

Assignees

• 昆明物理研究所

Dates

Publication Date

20260512

Application Date

20230224

Claims (6)

1. 1. The method is characterized in that the method is realized through two MicroBlaze soft cores in an FPGA chip, wherein MicroBlaze_0 soft cores control data transmission and storage processes, and MicroBlaze_1 soft cores control program data curing processes and logic control; The hardware platform applied by the method needs to comprise an FPGA chip, a PHY chip, a FLASH chip and a DDR chip; The FLASH chip storage is divided into two parts of bootloader_area and update_area; The bootloader_area comprises a network port data communication program, a data solidification program and a hot start jump program; For the MicroBlaze_0 soft core control data transmission and storage flow, an upper computer transmits an executable program file to be updated to the MicroBlaze_0 soft core through an Ethernet port, and the soft core checks data and writes the data into DDR storage after receiving effective data through the network port; For the MicroBlaze_1 soft core control program data curing process, monitoring whether data exists in DDR storage or not during the MicroBlaze_1 soft verification, and writing executable file data into a FLASH chip by performing read-write, check and rewrite operations on the data through a FLASH control programming module; The program update of the FPGA chip comprises updating executable file data in an update_area and correcting program data in a bootloader_area; if the upper computer is not confirmed to be connected to the network, executing a hot start jump program after 5s, then jumping to the update_area, and reading executable file data in the area to the FPGA chip for running; if the upper computer confirms that the network is connected, the program in the bootloader_area is continuously operated, after the update of the program data in the update_area is completed, the upper computer operates to enter a hot start jump program, executable file data in the area is read to operate in the FPGA chip, the bootloader_area position is designated by the upper computer, and the program data in the bootloader_area is updated.
2. 2. The method for loading, curing and updating the FPGA program implemented by the dual soft core according to claim 1, wherein the microblaze_0 soft core controls the thread to implement the ethernet interface to perform data communication with the host computer.
3. 3. The method for loading, curing and updating the FPGA program implemented by the dual soft core according to claim 1, wherein the microblaze_1 soft core is implemented by the thread to write the executable file data into the FLASH chip.
4. 4. The method for loading, solidifying and updating the FPGA program realized by the double soft cores according to claim 1, wherein the data transmission speed of the Ethernet is faster than the data writing speed of FLASH firmware, and the data received through the network port is temporarily stored in the DDR memory.
5. 5. The method for loading, curing and updating an FPGA program implemented by dual soft cores according to claim 1, wherein updating the executable file in the update_area comprises the following steps: (1) Running a program in a bootloader_area; (2) The upper computer confirms the connection network, and interrupts the hot start jump program; (3) Erasing executable file data in the update_area; (4) Reading new executable file data from the DDR storage and solidifying the new executable file data into an update_area; (5) And checking is passed, and updating is completed.
6. 6. The method for loading, curing and updating an FPGA program implemented by dual soft cores according to claim 1, wherein updating the executable file in the bootloader_area comprises the following steps: (1) Running a program in a bootloader_area; (2) The upper computer confirms the connection network, and interrupts the hot start jump program; (3) Erasing executable file data in a bootloader_area; (4) Reading new executable file data from the DDR storage and solidifying the new executable file data into a bootloader_area; (5) And checking is passed, and updating is completed.

Description

Method for loading, solidifying and updating FPGA program realized by double soft cores Technical Field The invention belongs to the technical field of software design of an embedded system with an FPGA as a framework, and particularly relates to a method for loading, solidifying and updating an FPGA program realized by double soft cores. Background The MicroBlaze embedded soft core is an RISC processor soft core which is optimized by Xilinx company and can be embedded in FPGA, has the advantages of high operation speed, less occupied resources, strong configurability and the like, and is widely applied to the fields of communication, military, high-end consumer markets and the like. MicroBlaze is a microprocessor IP core based on an FPGA of Xilinx company, and can complete the design of a programmable system chip (SOPC) together with other peripheral IP cores. The MicroBlaze processor uses the 32-bit instruction and data buses of the RISC architecture and the harvard architecture to execute programs stored in on-chip memory and external memory at full speed and access their data. In the fields of aerospace, industrial control, infrared detection, radar and the like, equipment with a Field Programmable Gate Array (FPGA) as a design scheme is widely used. The FPGA has the characteristics of high-speed data acquisition and transmission, good real-time performance, greater parallelism, complex logic control and the like, and can realize various control and communication protocols for peripheral equipment. Typically, these devices require constant updating of the complete system software. For large systems with multiple devices, if the system software is updated by way of the JTAG interface connection emulator, operations such as opening the device housing, disconnecting the connection cable, etc. are required. The software upgrading is carried out on all the boards which are connected with the simulators one by one, so that the time and the labor are consumed, and the risk of changing the state of the equipment is high, and the maintenance and the management of the equipment are not facilitated. Meanwhile, as the MicroBlaze embedded soft core processes data to run in a single-thread mode, the existing program solidification technology has a slower writing speed in a mode of executing operation sequences such as data transmission, data storage, FLASH writing, program jumping and the like, so that a quicker and more effective method is needed to finish the software program upgrading and loading function of the equipment board card, and therefore, development of a method for loading, solidifying and updating the FPGA program realized by double soft cores is needed to solve the problems. Disclosure of Invention Aiming at the technical defects of loading, solidifying and updating the program through the network port, the invention provides a method for loading, solidifying and updating the FPGA program realized by double soft cores. Aiming at the requirement of updating the board program conveniently and quickly through a network port, the invention verifies the multithreading operation of the program by using a plurality of MicroBlaze soft-check modules. The MicroBlaze_0 thread finishes data transmission to a storage space through a network port and finishes data check and retransmission work, and the MicroBlaze_1 thread is responsible for finishing reading the data in the storage space and writing the data into FLASH firmware and finishing the FLASH firmware writing data check and retransmission work. Because the time consumed for writing and reading the data of the FLASH firmware is relatively long, the MicroBlaze_0 thread can finish the related operations of data transmission and data storage in the process of data solidification of the MicroBlaze_1 thread. Compared with a MicroBlaze soft core single-thread sequential execution program curing process, the method saves time required by data transmission and storage, and achieves the purpose of more rapidly and effectively completing the software program upgrading of the equipment board card. The invention designs a corresponding FPGA network port loading program upper computer platform aiming at the network port program curing process. The platform can set the writing position of FLASH firmware autonomously, prompts whether the writing position is allowed or not in a display frame, re-inputs a new value if the writing position is not allowed, then sends the effective executable file data through a network port, returns a state value through the network port, and monitors the sending of the executable file data and the progress of the program curing process of the FLASH firmware in real time. According to the method, the method is realized through the transmission and storage processes of data by two MicroBlaze soft cores in an FPGA chip, the data solidification process and logic control of a MicroBlaze_1 soft core control program, a hardware platform applied to