CN-116302112-B - Low-power-consumption branch target buffer with two-stage prediction mechanism and design method

CN116302112BCN 116302112 BCN116302112 BCN 116302112BCN-116302112-B

Abstract

The invention discloses a low-power-consumption branch target buffer with a two-stage prediction mechanism, and relates to the technical field of processors. The system comprises a M-BTB module, a V-BTB module and a decision module, wherein the M-BTB module is connected in series and comprises a M-BTB prediction mechanism and a M-BTB structure, an input current instruction address predicts a target instruction address to store a potential Bank in the M-BTB structure through the M-BTB prediction mechanism, the V-BTB module comprises a V-BTB prediction mechanism and a V-BTB structure, the input current instruction address predicts the target instruction address to store a potential Way in the V-BTB structure through the V-BTB prediction mechanism, and the decision module checks the target instruction address output by the M-BTB module and the target instruction address of the V-BTB module. The invention reduces the query power consumption of the current instruction address for accessing the BTB structure through the prediction of the two-stage prediction mechanism to the Bank and Way.

Inventors

Nian Jiawei
LIU HONGJIN
Liang Zongnan
YANG MENGFEI
ZHANG SHAOLIN
GAO XIN
GAO JIAXUAN
YANG YINAN

Assignees

北京轩宇空间科技有限公司

Dates

Publication Date: 20260508
Application Date: 20230203

Claims (8)

1. A low-power branch target buffer with a two-stage prediction mechanism is characterized by comprising a M-BTB module, a V-BTB module and a decision module which are connected in series, The M-BTB module comprises a serial connection M-BTB prediction mechanism and an M-BTB structure, the M-BTB structure comprises 4 banks, the input current instruction address predicts a potential Bank stored in the M-BTB structure by the M-BTB prediction mechanism, and the current instruction address accesses the Bank; The V-BTB module comprises a V-BTB prediction mechanism and a V-BTB structure, the V-BTB structure comprises 4 Way, the input current instruction address predicts that the target instruction address stores potential Way in the V-BTB structure through the V-BTB prediction mechanism, and the current instruction address accesses the Way; The decision module is used for checking the target instruction address output by the M-BTB module and the target instruction address of the V-BTB module; The M-BTB prediction mechanism comprises a second decoder and a fourth decoder, wherein the second decoder decodes 2 bits of a current instruction address and a target instruction address in an M-BTB structure to obtain a corresponding Bank, the corresponding Bank is stored in the corresponding Bank, the 2 bits of the input current instruction address are decoded by the second decoder and the fourth decoder to obtain a target instruction address storage potential Bank, and the input current instruction address accesses the Bank; the V-BTB prediction mechanism comprises PARTIAL TAG tables, PARTIAL TAG tables comprise 2K table entries, the length of each table entry is 32 bits, each table entry is divided into A, B, C and D, the current instruction addresses of 4 Way are respectively corresponding to the current instruction addresses of 4 Way, 8 bits of the current instruction addresses of the 4 Way are selected, and the current instruction addresses are mapped to A, B, C and D in PARTIAL TAG; The PARTIAL TAG table sequentially corresponds to 4 Way in the V-BTB, 8 bits of the input current instruction address are matched with the PARTIALTAG table, and the matched Way is selected for access; The V-BTB contains 8K entries, divided into 4 Way, each Way containing 2K entries.
2. The low power branch target buffer with two-stage prediction mechanism according to claim 1, wherein the M-BTB structure is fully associative with 40 entries, divided into 4 banks, each Bank containing 10 entries.
3. The method for designing a low power branch target buffer with a two-stage prediction mechanism according to claim 1, comprising the steps of: step S1, inputting a current instruction address, accessing an M-BTB module, accessing an M-BTB structure according to the prediction result of an M-BTB prediction mechanism, if the input current instruction address hits the M-BTB structure, performing step S2, and if the input current instruction address does not hit the M-BTB structure, performing step S3; Step S2, determining that the input current instruction is a branch instruction, outputting a target instruction address PC1 by the M-BTB structure, comparing the target instruction address PC1 with a target instruction address PC3 output by the decision module, if the PC3 is the same as the PC1, the prediction result of the M-BTB module is correct, and redirection is not needed, otherwise, if the PC2 is different from the PC1, the prediction result of the M-BTB module is wrong, and redirection is needed; Step S3, the input current instruction address accesses the V-BTB module, accesses the V-BTB structure according to the prediction result of the V-BTB prediction mechanism, if the input current instruction address hits the V-BTB structure, the step S4 is performed, if the input current instruction address does not hit the V-BTB structure, the step S5 is performed; step S4, outputting a target instruction address PC2, comparing the target instruction address PC2 with a target instruction address PC3 output by the decision module, if the PC2 is the same as the PC3, the prediction result of the V-BTB module is correct, and redirection is not needed, otherwise, if the PC2 is different from the PC3, the prediction result of the V-BTB module is incorrect, and redirection is needed; And S5, determining that the current instruction is a sequential execution instruction, and not checking through the decision module, wherein the prediction result of the M-BTB module is wrong, and the redirection is not performed.
4. The method for designing a low power branch target buffer with a two-stage prediction mechanism as recited in claim 3, wherein the redirecting includes sending the target instruction address PC3 to the PC register, returning the current instruction address and the target instruction address PC3 checked by the decision module to the M-BTB module, and updating the M-BTB module.
5. The method of claim 3, wherein the step S3 is performed to access the V-BTB module while sequentially increasing the input current instruction address to be the target instruction address PC1, and returning to the PC register for further fetching.
6. The method for designing a low-power branch target buffer with a two-stage prediction mechanism according to claim 3, wherein the step S1 specifically comprises: and 2 bits of the input current instruction address are input into an M-BTB prediction mechanism, the M-BTB prediction mechanism predicts a target instruction address storage potential Bank in the M-BTB structure, the target instruction address storage potential Bank in the M-BTB structure is selected by using the current instruction address and accessed, and if the input current instruction address is successfully matched with the Bank table entry, the target instruction address hits the Bank, namely, the current instruction address hits the M-BTB structure.
7. The method of claim 3, wherein the M-BTB prediction mechanism is a bi-quad decoder, the 2-bit address is decoded to obtain 4-bit index, 4 banks in the M-BTB structure are accessed, each Bank corresponds to 0001, 0010, 0100, 1000, and the current instruction address and the target instruction address in the M-BTB structure are decoded by the bi-quad decoder, and the decoded corresponding banks are selected for storage.
8. The method for designing a low power consumption branch target buffer with two-stage prediction mechanism according to claim 3, wherein the step S4 specifically comprises: The input current instruction address is input into a V-BTB prediction mechanism, the V-BTB prediction mechanism is a PARTIAL TAG table, a PARTIAL TAG table sequentially corresponds to 4 Way in the V-BTB, 8 bits of the input current instruction address are matched with the PARTIAL TAG table, the matched Way is selected for access, and if the input current instruction address is successfully matched with the current instruction address in the Way table entry, the hit of the Way is indicated, namely the hit of the current instruction address to the V-BTB structure is indicated.

Description

Low-power-consumption branch target buffer with two-stage prediction mechanism and design method Technical Field The invention relates to the technical field of processors, in particular to a low-power-consumption branch target buffer with a two-stage prediction mechanism and a design method thereof. Background Processor design is an engineering task to design critical components contained in a computer. The branch prediction module is one of the key modules in the processor core. The performance of branch prediction determines whether a processor can continue to fetch instruction addresses for instruction fetching. BTB (branch target buffer) is one of the core components in the branch prediction module and is critical to processor branch prediction performance. The BTB includes a current instruction address, a target instruction address, and an instruction type. The current instruction address accesses the BTB structure, if the instruction address hits, the instruction is considered a branch instruction, and the stored target instruction address is output. Otherwise, the current instruction address is considered to be missed. As the complexity of programs increases, so does the processor performance requirements. In order to meet the execution requirements of more complicated programs, the capacity of BTB structures is gradually expanding, resulting in an increase in query power consumption of BTB modules. The BTB power consumption was found to be 7.4% of the total processor power consumption from previous statistics. Disclosure of Invention The invention aims to provide a low-power-consumption branch target buffer with a two-stage prediction mechanism and a design method thereof, wherein the potential storage positions of target instruction addresses in an M-BTB structure and a V-BTB are predicted by the two-stage prediction mechanism, so that the query power consumption of the current instruction address for accessing the BTB structure is reduced, and the problem that the query power consumption of a BTB module is increased due to the gradual expansion of the capacity of the BTB structure in the background technology is solved. The technical scheme adopted by the invention is as follows: The invention relates to a low-power consumption branch target buffer with a two-stage prediction mechanism, which comprises an M-BTB module, a V-BTB module and a decision module which are connected in series, The M-BTB module comprises a serial connection M-BTB prediction mechanism and an M-BTB structure, the M-BTB structure comprises 4 banks, the input current instruction address predicts a potential Bank stored in the M-BTB structure by the M-BTB prediction mechanism, and the current instruction address accesses the Bank; The V-BTB module comprises a V-BTB prediction mechanism and a V-BTB structure, the V-BTB structure comprises 4 Way, the input current instruction address predicts that the target instruction address stores potential Way in the V-BTB structure through the V-BTB prediction mechanism, and the current instruction address accesses the Way; And the decision module is used for checking the target instruction address output by the M-BTB module and the target instruction address of the V-BTB module. Further, the M-BTB prediction mechanism includes a bi-quad decoder, where the bi-quad decoder decodes the current instruction address in the M-BTB structure and 2 bits of the target instruction address to obtain a corresponding Bank, stores the corresponding Bank, decodes the 2 bits of the input current instruction address through the bi-quad decoder to obtain a target instruction address storage potential Bank, and accesses the Bank by the input current instruction address. Further, the M-BTB structure is a fully-connected structure of 40 entries, and is divided into 4 banks, wherein each Bank comprises 10 entries. Further, the V-BTB prediction mechanism includes PARTIAL TAG table, PARTIAL TAG table includes 2K entries, the length of a single entry is 32 bits, and the entries are divided into a, B, C, and D, respectively corresponding to current instruction addresses of 4 Way, 8 bits of which are selected, and mapped to a, B, C, and D in PARTIAL TAG; The PARTIAL TAG table sequentially corresponds to 4 Way in the V-BTB, 8 bits of the input current instruction address are matched with the PARTIAL TAG table, and the matched Way is selected for access; The V-BTB contains 8K entries, divided into 4 Way, each Way containing 2K entries. A design method of a low-power-consumption branch target buffer with a two-stage prediction mechanism comprises the following steps: step S1, inputting a current instruction address, accessing an M-BTB module, accessing an M-BTB structure according to the prediction result of an M-BTB prediction mechanism, if the input current instruction address hits the M-BTB structure, performing step S2, and if the input current instruction address does not hit the M-BTB structure, performing step S3