CN-116312324-B - Shift register, display driver and display panel

Abstract

The invention discloses a shift register, a display driver and a display panel. The shift register comprises a first input module, a second input module, a control module and an output module, wherein the second input module is electrically connected with a shift input end, a first clock input end and a second control end of the shift register, adjusts the potential of the second control end according to an input signal of the shift input end and a first clock signal, and is electrically connected with the second clock input end, a second voltage input end, the shift control end and the first control end of the output module, and is configured to input a second voltage signal of the second voltage input end to the first control end of the output module according to the second clock signal and the shift control signal of the shift control end when the shift output end of the shift register outputs the first voltage signal. The invention can improve the ripple problem of the existing shift register.

Inventors

• Sang Chengxiang
• ZHANG LU

Assignees

• 合肥维信诺科技有限公司
• 昆山国显光电有限公司

Dates

Publication Date

20260512

Application Date

20230324

Claims (20)

1. 1. The shift register is characterized by comprising a first input module, a second input module, a control module and an output module; The first input module is electrically connected with a first voltage input end, a first clock input end, a second clock input end and a first control end of the output module, and is configured to adjust the potential of the first control end according to a first clock signal of the first clock input end, a second clock signal of the second clock input end and a first voltage signal of the first voltage input end; The second input module is electrically connected with the shift input end of the shift register, the first clock input end and the second control end of the output module, and is configured to adjust the potential of the second control end according to the input signal of the shift input end and the first clock signal; The output module is electrically connected with the first voltage input end, the second voltage input end and the shift output end of the shift register and is configured to output a first voltage signal of the first voltage input end to the shift output end of the shift register according to the potential of the first control end; The control module is electrically connected with the second clock input end, the second voltage input end, the shift control end and the first control end and is configured to input a second voltage signal of the second voltage input end to the first control end according to the second clock signal and a shift control signal of the shift control end when the shift output end of the shift register outputs the first voltage signal; The control module comprises a first control unit and a second control unit; The first control unit and the second control unit are connected in series between the second voltage input end and the first control end, the control end of the first control unit is electrically connected with the shift control end, and the control end of the second control unit is electrically connected with the second clock input end; The turn-on level of the second control unit is opposite to the logic of the second voltage signal.
2. 2. The shift register according to claim 1, wherein the first control unit includes an eighth transistor, a first terminal of the eighth transistor being a first terminal of the first control unit, a second terminal of the eighth transistor being a second terminal of the first control unit, a control terminal of the eighth transistor being a control terminal of the first control unit.
3. 3. The shift register according to claim 1, wherein the second control unit includes a ninth transistor, a first terminal of the ninth transistor being a first terminal of the second control unit, a second terminal of the ninth transistor being a second terminal of the second control unit, and a control terminal of the ninth transistor being a control terminal of the second control unit.
4. 4. The shift register of claim 1, wherein the active level of the first control terminal is opposite to the logic of the second voltage signal at the second voltage input terminal; The pulse end time of the shift control signal is later than the pulse start time of the first effective pulse of the second clock signal and earlier than the pulse start time of the second effective pulse of the second clock signal in the effective level time of the input signal.
5. 5. The shift register of claim 4, wherein a pulse start time of the shift control signal is the same as a pulse start time of the input signal.
6. 6. The shift register of claim 4, wherein the duration of the active pulses at the shift input and shift output of the shift register is greater than the period of the second clock signal.
7. 7. The shift register of claim 4, wherein the duration of the active pulse at the shift input and shift output of the shift register is greater than the duration of the active pulse of the shift control signal.
8. 8. The shift register of claim 4, wherein a duration of an active pulse of the shift control signal is greater than a duration of an active level of the second clock signal.
9. 9. The shift register of claim 1, wherein the first input module comprises: the device comprises a power supply introduction unit, a first adjusting unit, a second adjusting unit and a coupling unit; The first end of the power supply introduction unit is electrically connected with the first voltage input end, the control end of the power supply introduction unit is electrically connected with the first clock input end, and the second end of the power supply introduction unit is electrically connected with the control end of the first regulating unit; the first end of the first regulating unit is electrically connected with the second clock input end, and the second end of the first regulating unit is electrically connected with the first end of the second regulating unit; the control end of the second regulating unit is electrically connected with the second clock input end, and the second end of the second regulating unit is electrically connected with the first control end; the first end of the coupling unit is electrically connected with the control end of the first adjusting unit, and the second end of the coupling unit is electrically connected with the second end of the first adjusting unit.
10. 10. The shift register of claim 9, wherein the first adjustment unit is configured to be turned on in response to a signal at a control terminal of the first adjustment unit, thereby transmitting a signal at a first terminal of the first adjustment unit to a second terminal of the first adjustment unit.
11. 11. The shift register of claim 9, wherein the power supply introduction unit is configured to be turned on in response to a signal of a control terminal of the power supply introduction unit, thereby transmitting a signal of a first terminal of the power supply introduction unit to a second terminal of the power supply introduction unit.
12. 12. The shift register of claim 9, wherein the second adjustment unit is configured to be turned on in response to a signal at a control terminal of the second adjustment unit, thereby transmitting a signal at a first terminal of the second adjustment unit to a second terminal of the second adjustment unit.
13. 13. The shift register of claim 9, wherein the coupling unit comprises a first capacitor having a first end as a first end of the coupling unit and a second end as a second end of the coupling unit.
14. 14. The shift register of claim 9, wherein the first adjustment unit comprises a sixth transistor, a first terminal of the sixth transistor being a first terminal of the first adjustment unit, a second terminal of the sixth transistor being a second terminal of the first adjustment unit, a control terminal of the sixth transistor being a control terminal of the first adjustment unit.
15. 15. The shift register according to claim 9, wherein the second adjusting unit comprises a seventh transistor, a first terminal of the seventh transistor being a first terminal of the second adjusting unit, a second terminal of the seventh transistor being a second terminal of the second adjusting unit, a control terminal of the seventh transistor being a control terminal of the second adjusting unit.
16. 16. The shift register of claim 9, further comprising a first feedback module electrically connected to the second control terminal, the first clock input terminal, and the second terminal of the power supply introduction unit, wherein the first feedback module is configured to write the first clock signal to the second terminal of the power supply introduction unit according to a potential of a terminal of the second input module connected to the second control terminal.
17. 17. The shift register of claim 16, wherein the first feedback block comprises a third transistor, a first terminal of the third transistor being a first terminal of the first feedback block, a second terminal of the third transistor being a second terminal of the first feedback block, a control terminal of the third transistor being a control terminal of the first feedback block.
18. 18. The shift register of claim 16, further comprising a second feedback module electrically connected to the second terminal of the power supply introduction unit, the second voltage input terminal, the second clock input terminal, and the second control terminal, the second feedback module configured to adjust the potential of the second control terminal according to the potential of the second terminal of the power supply introduction unit, the second clock signal, and the first voltage signal.
19. 19. The shift register of claim 18, wherein the power supply introduction unit comprises a first transistor, a first terminal of the first transistor being a first terminal of the power supply introduction unit, a second terminal of the first transistor being a second terminal of the power supply introduction unit, and a control terminal of the first transistor being a control terminal of the power supply introduction unit.
20. 20. The shift register of claim 19, wherein the second feedback module comprises a fourth transistor, a fifth transistor, and a third capacitor, wherein a first end of the fourth transistor is electrically connected to the second voltage input terminal, a second end of the fourth transistor is electrically connected to the first end of the fifth transistor, a control end of the fourth transistor is electrically connected to the second end of the first transistor, a second end of the fifth transistor is electrically connected to the second clock input terminal, a control end of the fifth transistor is electrically connected to the second control end, a first end of the third capacitor is electrically connected to the second end of the fourth transistor, and a second end of the third capacitor is electrically connected to the second control end.

Description

Shift register, display driver and display panel Technical Field The present invention relates to the field of display technologies, and in particular, to a shift register, a display driver, and a display panel. Background Along with the development of display technology, the application of display panels is also becoming wider, and the corresponding requirements on the display panels are also becoming higher. Various scanning signals required during pixel display are required to be provided in the display panel through the shift register, however, when the existing shift register outputs a pulse with a longer duration, a ripple phenomenon occurs, so that charging effects of each row in the display panel are inconsistent, and brightness difference occurs in the display panel. Disclosure of Invention The invention provides a shift register, a display driver and a display panel, which are used for improving the ripple problem of the existing shift register. According to an aspect of the present invention, there is provided a shift register including a first input module, a second input module, a control module, and an output module; The first input end module is electrically connected with the first voltage input end, the first clock input end, the second clock input end and the first control end of the output module and is configured to adjust the potential of the first control end according to the first clock signal of the first clock input end, the second clock signal of the second clock input end and the first voltage signal of the first voltage input end; The second input module is electrically connected with the shift input end of the shift register, the first clock input end and the second control end of the output module and is configured to adjust the potential of the second control end according to the input signal of the shift input end and the first clock signal; The output module is electrically connected with the first voltage input end, the second voltage input end and the shift output end of the shift register and is configured to output a first voltage signal of the first voltage input end to the shift output end of the shift register according to the potential of the first control end; The control module is electrically connected with the second clock input end, the second voltage input end, the shift control end and the first control end and is configured to input a second voltage signal of the second voltage input end to the first control end according to the second clock signal and the shift control signal of the shift control end when the shift output end of the shift register outputs the first voltage signal. Optionally, the control module comprises a first control unit and a second control unit; the first control unit and the second control unit are connected in series between the second voltage input end and the first control end, the control end of the first control unit is electrically connected with the shift control end, and the control end of the second control unit is electrically connected with the second clock input end; optionally, the on level of the second control unit is opposite to the logic of the second voltage signal. Optionally, the active level of the first control terminal is opposite to the logic of the second voltage signal of the second voltage input terminal; The pulse end time of the shift control signal is later than the pulse start time of the first effective pulse of the second clock signal and earlier than the pulse start time of the second effective pulse of the second clock signal in the effective level time of the input signal Optionally, the pulse start time of the shift control signal is the same as the pulse start time of the input signal; Optionally, the duration of the active pulses at the shift input and the shift output of the shift register is greater than the period of the second clock signal; Optionally, the duration of the active pulse at the shift input and the shift output of the shift register is greater than the duration of the active pulse of the shift control signal. Optionally, the first input module includes: the device comprises a power supply introduction unit, a first adjusting unit, a second adjusting unit and a coupling unit; The first end of the power supply introduction unit is electrically connected with the first voltage input end, the control end of the power supply introduction unit is electrically connected with the first clock input end, and the second end of the power supply introduction unit is electrically connected with the control end of the first regulating unit; The first end of the first regulating unit is electrically connected with the second clock input end, and the second end of the first regulating unit is electrically connected with the first end of the second regulating unit; The control end of the second regulating unit is electrically connected with the second clock input end, and the second end of the sec