CN-116314126-B - Bottom lead-out terminal non-airtight packaging SiP module

CN116314126BCN 116314126 BCN116314126 BCN 116314126BCN-116314126-B

Abstract

The invention provides a bottom lead-out end non-airtight packaging SiP module which comprises a packaging base, an adapter plate, a chip stacking body, a plastic package body and a chip stacking body, wherein the packaging base comprises pins and a bottom plate, one end of each pin is fixed on the upper surface of the bottom plate, the other end of each pin is led out from the lower surface of the bottom plate, the adapter plate comprises a wiring layer, a substrate layer and a first electric interconnection structure, the substrate layer is adhered to the surface of the packaging base, the wiring layer is prepared on the upper surface of the substrate layer, the wiring layer and the pins are interconnected through the first electric interconnection structure, the chip stacking body comprises bare chips, an adhesive layer and a second interconnection structure, the bare chips positioned at the bottommost layer are formed on the upper surface of the adapter plate through the adhesive layer, the second bare chips and the higher bare chips are all formed on the upper surface of the next bare chips through the adhesive layer, the bare chips and the wiring layer are interconnected through the second electric interconnection structure, and the upper half part of each pin, the adapter plate and the chip stacking body are encapsulated inside the chip stacking body and are formed into a whole body with the bottom plate. The invention can improve the reliability between the SiP module and the circuit board.

Inventors

LIU MIFENG
LUO JIANGBO
TANG ZHIYI
XIE YA
DAI JIE
SUN SHUDAN
CHEN KAI

Assignees

上海航天电子通讯设备研究所

Dates

Publication Date: 20260505
Application Date: 20230220

Claims (11)

1. The non-airtight packaging SiP module with the bottom leading-out end is characterized by comprising a packaging base, an adapter plate, a chip stacking body and a potting body; the packaging base comprises pins and a bottom plate, wherein the pins penetrate through grooves or through holes of the bottom plate, one end of each pin is fixed on the upper surface of the bottom plate, and the other end of each pin is led out from the lower surface of the bottom plate; The adapter plate comprises a wiring layer, a substrate layer and a first electric interconnection structure, wherein the substrate layer is adhered to the surface of the packaging base, the wiring layer is prepared on the upper surface of the substrate layer, and the wiring layer and the pins are electrically interconnected through the first electric interconnection structure; The chip stack body comprises a plurality of bare chips, an adhesive layer and a second electric interconnection structure, wherein the bare chips positioned at the bottommost layer are formed on the upper surface of the adapter plate through the adhesive layer, the second-layer bare chips and the higher-layer bare chips are all formed on the upper surface of the next-layer bare chip through the adhesive layer, and the bare chips and the wiring layer are electrically interconnected through the second electric interconnection structure; the plastic package body is used for packaging the upper half part of the pin, the adapter plate and the chip stacking body in the plastic package body and is integrated with the bottom plate; the surface of the pouring body is covered with a grounded metal film layer, and the metal film layer structure adopts any one of Ni/Au alloy, ni/Pb/Au alloy, cr/Au alloy and Ti/Au alloy.
2. The bottom dead-end non-hermetically sealed SiP module of claim 1, wherein the leads are made of at least one of copper alloy and iron-nickel alloy.
3. The bottom dead-end non-hermetically packaged SiP module of claim 1, wherein the bottom plate is at least any one of a chip carrier, a PCB, a ceramic substrate, a co-fired ceramic substrate, a glass substrate, and a quartz substrate.
4. The bottom-pigtail non-hermetically packaged SiP module of claim 1, wherein the wiring layer employs any one of PI/Cu thin film wiring, BCB/Cu wiring, and SiO 2 /Cu wiring.
5. The bottom dead-end non-hermetically packaged SiP module of claim 1, wherein the interposer substrate layer is employed with any one of silicon, glass, quartz, and an organic carrier.
6. The bottom-pigtail non-hermetically packaged SiP module of claim 1, wherein the first electrical interconnect structure employs any one of wire bonding and solder interconnection.
7. The bottom-pigtail non-hermetically packaged SiP module of claim 1, wherein the die-type of die-stack employs any one of a digital-type die, an analog-type die, a radio-frequency-type die, a hybrid integrated-type die, and a MEMS die.
8. The bottom-lead non-hermetically packaged SiP module of claim 1, wherein the stacked configuration of the chip stack employs stacking of layers, pyramids, and/or steps.
9. The bonding between die in the die stack of claim 8 using either one of an adhesive film patch and an epoxy patch.
10. The bottom dead-end non-hermetically packaged SiP module of claim 1, wherein the second electrical interconnect structure is in the form of any one of wire bonding and solder interconnect.
11. The bottom dead-end non-hermetically packaged SiP module of claim 1, wherein the potting material is any one of epoxy, silicone, and polyurethane.

Description

Bottom lead-out terminal non-airtight packaging SiP module Technical Field The invention relates to the technical field of system-in-package and advanced packaging, in particular to a bottom lead-out end non-airtight packaging SiP module. Background With the rapid development of electronic products toward miniaturization and integration, system In Package (SiP) technology is one of the important directions of future development of the microelectronics industry. The SiP technology realizes high-density integrated integration of a plurality of heterogeneous bare chips or devices in one package body through various advanced packaging technologies. Therefore, the SiP module product not only has the advantages of miniaturization, multifunction, high reliability and the like, but also can reduce the design difficulty of the rear end ring section, shorten the product development period, reduce the management cost of a supply chain and the like. The current SiP module products basically adopt device grade standards for quality assessment, and the interface form is consistent with or compatible with the device interface of the conventional package. A large number of electrical interconnections of SiP modules have been completed inside packages and have been part of interactions between subsystems when interacting with external functions, so SiP modules typically only require tens to hundreds of I/O interfaces, with the pitch of the I/O interfaces typically ranging from sub-millimeter to millimeter in size. With respect to the number and size characteristics of the I/O interfaces described above, siP modules can generally be used in a split into a leaded package situation typically represented by SOP and a leadless form typically represented by BGA. In severe environments such as aerospace, weaponry and the like, the SiP module is subjected to severe mechanical impact and thermal stress impact caused by extreme temperature change. Under such severe application environments, the SiP products claimed in patents such as CN202011323589, CN202110140717, CN201810154887, CN201420433174, etc. employ package interface forms such as BGA, QFN, etc., and serious electrical interconnection reliability problems are faced. And the SiP product with the pins can play a role in buffering stress because of the metal pins between the device packaging body and the PCB, and the reliability of the whole system can be greatly improved. If the SiP module adopts a conventional leaded package structure represented by SOP, QFP, etc., the lead-out terminal of the lead is on the side of the device, the contact area between the lead and the PCB motherboard pad is generally only 0.5 mm-1 mm long, which cannot meet the high reliability application requirement. If the welding length of the pins and the PCB motherboard is increased, the whole area of the SiP module is greatly increased, and the real miniaturization target cannot be realized. Therefore, the pins are led out from the bottom of the module, and the welding length of the pins and the PCB motherboard can be increased by a plurality of times while the area of the SiP module is not increased, so that the SiP module and the PCB motherboard are really and reliably connected mechanically. Currently, france 3D plus and zhuhai euro bit companies stack and integrally encapsulate a plurality of SOP packages and a lead frame in a bottom lead-out form, then interconnect through metal thin film wires on the sides of the encapsulant, and finally obtain a bottom lead-out non-hermetically encapsulated SiP module based on PoP packaging technology, which has been applied in aerospace products. However, since the PoP package technology adopts devices to stack, the thickness of the PoP package SiP module is very large, which is generally equal to 1 to 1.5 times of the sum of the thicknesses of all devices. The SiP module has larger mass, and can generate larger impact force on the bottom pins in a vibration environment, so that the pins of the SiP module are welded and cracked to cause abnormal electrical interconnection, even the whole SiP module falls off from the PCB module, and the function of the whole single-machine system is disabled. Disclosure of Invention Aiming at the defects in the prior art, the invention aims to provide a non-airtight packaging SiP module with a bottom leading-out end, a plurality of bare chips can be stacked in the module, and an adapter plate with a high-density wiring layer is adopted to solve the contradiction problem between the complex electrical interconnection requirement of the stacked bare chips and the simple interconnection capability of a lead frame, and meanwhile, the whole volume and the weight can be further improved, so that the interconnection reliability between the SiP module and a single PCB mother board is obviously improved. The invention provides a bottom leading-out end non-airtight packaging SiP module, which comprises a packaging base, an adapter plate