CN-116317579-B - Logic circuit for DC-DC converter and DC-DC converter

CN116317579BCN 116317579 BCN116317579 BCN 116317579BCN-116317579-B

Abstract

Embodiments of the present disclosure provide a logic circuit for a DC-DC converter and a DC-DC converter. The logic circuit comprises a head step detection circuit, an upper pipe turn-off control circuit and a lower pipe turn-off control circuit. The first step detection circuit is configured to detect a first step of an output voltage of the DC-DC converter in a soft start stage according to one of an upper pipe shut-off signal output by the upper pipe shut-off control circuit and a lower pipe shut-off signal output by the lower pipe shut-off control circuit, a feedback voltage of the DC-DC converter, and a first reference voltage from a first reference voltage terminal to generate a first step indication signal. The upper tube turn-off control circuit is configured to cause the upper tube turn-off signal to be at an active level to indicate turn-off of the upper tube of the DC-DC converter if the first step indication signal is at an active level. The down tube shutdown control circuit is configured to cause the down tube shutdown signal to be at an active level to indicate shutdown of the down tube of the DC-DC converter if the first step indication signal is at an active level.

Inventors

LIU WEIBO
MA MENGJIAO

Assignees

骏盈半导体(上海)有限公司

Dates

Publication Date: 20260508
Application Date: 20230323

Claims (9)

1. A logic circuit for a DC-DC converter includes a head-step detection circuit, an upper-tube turn-off control circuit, and a lower-tube turn-off control circuit, The first step detection circuit is configured to detect a first step of an output voltage of the DC-DC converter in a soft start stage according to one of an upper pipe shut-off signal output by the upper pipe shut-off control circuit and a lower pipe shut-off signal output by the lower pipe shut-off control circuit, a feedback voltage of the DC-DC converter, and a first reference voltage from a first reference voltage terminal to generate a first step indication signal; the upper tube turn-off control circuit is configured to make the upper tube turn-off signal at an active level to indicate turn-off of an upper tube of the DC-DC converter in a case that the first step indication signal is at an active level; The down tube turn-off control circuit is configured to cause the down tube turn-off signal to be at an active level to indicate turn-off of a down tube of the DC-DC converter in a case where the first step indication signal is at an active level; Wherein the first step detection circuit comprises a ramp signal generation circuit, a starting control circuit, a first RS trigger, an error amplifier and an output circuit, The ramp signal generating circuit is configured to generate a ramp signal; The start-up control circuit is configured to generate a start-up detection signal from the ramp signal and the first reference voltage, wherein the start-up detection signal is at a first level when the ramp signal is lower than the first reference voltage, and the start-up detection signal is flipped to a second level when the ramp signal is raised to the first reference voltage; The set end of the first RS trigger is provided with the starting detection signal, the reset end of the first RS trigger is provided with one of the lower pipe shut-off signal and the upper pipe shut-off signal, and a first enabling signal is output from the output end of the first RS trigger; The first input end of the error amplifier is provided with the ramp signal, the second input end of the error amplifier is provided with the feedback voltage, and a soft start control signal is output from the output end of the error amplifier; The output circuit is configured to cause the first step indication signal to be at an active level if both the soft start control signal and the first enable signal are at an active level.
2. The logic circuit of claim 1, wherein the start-up control circuit comprises a voltage comparator and a first inverter, Wherein a first input end of the voltage comparator is provided with the ramp signal, a second input end of the voltage comparator is coupled with the first reference voltage end, and an output end of the voltage comparator is coupled with an input end of the first inverter; the output end of the first inverter is coupled with the set end of the first RS trigger.
3. The logic circuit of claim 1, wherein the start-up control circuit comprises a voltage comparator, The first input end of the voltage comparator is coupled to the first reference voltage end, the second input end of the voltage comparator is provided with the ramp signal, and the output end of the voltage comparator is coupled to the set end of the first RS trigger.
4. The logic circuit of claim 1, wherein the ramp signal generating circuit comprises a first current source, and a first capacitor, Wherein the first current source is configured to provide a first current to a first terminal of the first capacitor; the second end of the first capacitor is coupled with a second voltage end; Wherein the ramp signal is generated at a first end of the first capacitor.
5. The logic circuit of claim 1, wherein the output circuit comprises a second inverter, and an AND gate, The input end of the second inverter is coupled with the output end of the error amplifier, and the output end of the second inverter is coupled with the first input end of the AND gate; The second input end of the AND gate is coupled with the output end of the first RS trigger, and the first step indication signal is output from the output end of the AND gate.
6. The logic circuit according to any one of claims 1 to 5, wherein the upper pipe turn-off control circuit comprises a second RS flip-flop, The setting end of the second RS trigger is provided with the first step indication signal, and the upper tube turn-off signal is output from the output end of the second RS trigger.
7. The logic circuit according to any one of claims 1 to 5, wherein the down tube turn-off control circuit comprises a delay circuit, and a third RS flip-flop, The delay circuit is configured to delay the first step indication signal to output a delayed first step indication signal; The setting end of the third RS trigger is provided with the delayed head step indication signal, and the down tube turn-off signal is output from the output end of the third RS trigger.
8. A logic circuit for a DC-DC converter includes a first current source, a first capacitor, a voltage comparator, a first inverter, a second inverter, an AND gate, an error amplifier, a first RS flip-flop, a second RS flip-flop, a third RS flip-flop, and a delay circuit, Wherein the first current source is configured to provide a first current to a first terminal of the first capacitor; the second end of the first capacitor is coupled with a second voltage end; The first input end of the error amplifier is coupled with the first end of the first capacitor, the second input end of the error amplifier is coupled with the feedback voltage end of the DC-DC converter, and the output end of the error amplifier is coupled with the input end of the second inverter; The first input end of the voltage comparator is coupled with the first end of the first capacitor, the second input end of the voltage comparator is coupled with the first reference voltage end, and the output end of the voltage comparator is coupled with the input end of the first inverter; the output end of the first inverter is coupled with the set end of the first RS trigger; The reset end of the first RS trigger is coupled with one of the output end of the second RS trigger and the output end of the third RS trigger; the output end of the second inverter is coupled with the first input end of the AND gate; the second input end of the AND gate is coupled with the output end of the first RS trigger, and the output end of the AND gate is coupled with the setting end of the second RS trigger and the delay circuit; outputting an upper tube turn-off signal from the output end of the second RS trigger; The delay circuit is configured to delay a first step indication signal output from the AND gate to output a delayed first step indication signal; the setting end of the third RS trigger is provided with the delayed first step indication signal, and a down tube turn-off signal is output from the output end of the third RS trigger; the effective level of the upper tube turn-off signal is used for indicating turn-off of an upper tube of the DC-DC converter, and the effective level of the lower tube turn-off signal is used for indicating turn-off of a lower tube of the DC-DC converter.
9. A DC-DC converter comprising the logic circuit according to any one of claims 1 to 8.

Description

Logic circuit for DC-DC converter and DC-DC converter Technical Field Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to a logic circuit for a DC-DC converter and a DC-DC converter. Background DC-DC (direct current-direct current) converters are widely used in various chip-powered applications. The DC-DC converter includes a BUCK converter (BUCK) and a BOOST converter (BOOST). The buck converter may convert a higher dc voltage to a lower dc voltage. The boost converter may convert a lower dc voltage to a higher dc voltage. During the power-up of the DC-DC converter, if its output voltage rises too fast, the DC-DC converter requires a lot of energy to the forward stage (the power supply stage of the DC-DC converter). In order to protect the power supply of the front stage, a soft start process is provided in the power-up process of the DC-DC converter. Soft start enables the output voltage of the DC-DC converter to rise from zero volts to a nominal value at a slower rate. In this way, the DC-DC converter slowly transfers energy without momentarily extracting too much energy from the input (pre-stage) to destroy the pre-stage. Disclosure of Invention Embodiments described herein provide a logic circuit for a DC-DC converter and a DC-DC converter. According to a first aspect of the present disclosure, a logic circuit for a DC-DC converter is provided. The logic circuit comprises a head step detection circuit, an upper pipe turn-off control circuit and a lower pipe turn-off control circuit. The first step detection circuit is configured to detect a first step of an output voltage of the DC-DC converter in a soft start stage according to one of an upper pipe shut-off signal output by the upper pipe shut-off control circuit and a lower pipe shut-off signal output by the lower pipe shut-off control circuit, a feedback voltage of the DC-DC converter, and a first reference voltage from a first reference voltage terminal to generate a first step indication signal. The upper tube turn-off control circuit is configured to cause the upper tube turn-off signal to be at an active level to indicate turn-off of the upper tube of the DC-DC converter if the first step indication signal is at an active level. The down tube shutdown control circuit is configured to cause the down tube shutdown signal to be at an active level to indicate shutdown of the down tube of the DC-DC converter if the first step indication signal is at an active level. In some embodiments of the present disclosure, a first step detection circuit includes a ramp signal generation circuit, a start control circuit, a first RS flip-flop, an error amplifier, and an output circuit. Wherein the ramp signal generating circuit is configured to generate the ramp signal. The start-up control circuit is configured to generate a start-up detection signal from the ramp signal and the first reference voltage. The start detection signal is at a first level when the ramp signal is lower than a first reference voltage. The start detection signal is flipped to a second level when the ramp signal rises to the first reference voltage. The set terminal of the first RS flip-flop is provided with a start-up detection signal. The reset terminal of the first RS flip-flop is provided with one of a down tube shutdown signal and an up tube shutdown signal. A first enable signal is output from an output terminal of the first RS flip-flop. A first input of the error amplifier is provided with a ramp signal. A second input of the error amplifier is provided with a feedback voltage. A soft start control signal is output from the output of the error amplifier. The output circuit is configured to cause the first step indication signal to be at an active level if both the soft start control signal and the first enable signal are at an active level. In some embodiments of the present disclosure, a start-up control circuit includes a voltage comparator, and a first inverter. Wherein a first input of the voltage comparator is provided with a ramp signal. The second input end of the voltage comparator is coupled with the first reference voltage end. The output end of the voltage comparator is coupled with the input end of the first inverter. The output end of the first inverter is coupled to the set end of the first RS flip-flop. In some embodiments of the present disclosure, the start-up control circuit includes a voltage comparator. The first input end of the voltage comparator is coupled to the first reference voltage end. A second input of the voltage comparator is provided with a ramp signal. The output end of the voltage comparator is coupled with the set end of the first RS trigger. In some embodiments of the present disclosure, a ramp signal generating circuit includes a first current source, and a first capacitor. Wherein the first current source is configured to provide a first current to a first terminal of the first cap