CN-116322028-B - Semiconductor structure, manufacturing method thereof and memory system

Abstract

The embodiment of the disclosure discloses a semiconductor structure, which comprises an active column array, a first storage structure, a second storage structure, a first bit line, a second bit line and a first active region, wherein the active column array comprises a first active column and a second active column which are arranged in an array mode, the first active column and the second active column are respectively arranged on two opposite sides of the channel region along a first direction, the first direction is the extending direction of the channel region, the word line surrounds the first active column and the second active column, the first storage structure is located on a first side of the active column array and is electrically connected with the first active region of the first active column, the second storage structure is located on a second side of the active column array and is electrically connected with the second active region of the second active column, the first side and the second side are opposite sides of the active column array along the first direction, the first bit line is located on the second side of the active column array and is connected with the second active region of the first active column, and the second bit line is located on the first side of the active column array and is connected with the first active region of the second active column.

Inventors

• HUA WENYU

Assignees

• 芯盟科技有限公司

Dates

Publication Date

20260508

Application Date

20221209

Claims (18)

1. 1. A semiconductor structure, comprising: The active column array comprises a first active column and a second active column which are arranged in an array manner, wherein the first active column and the second active column both comprise a channel region, a first active region and a second active region which are respectively positioned at two opposite ends of the channel region along a first direction, the first direction is the extending direction of the channel region, the first active column and the second active column form a plurality of columns of active columns arranged along a second direction and a plurality of rows of active columns arranged along a third direction, each row of active columns comprises the first active columns and the second active columns which are alternately arranged, and each column of active columns comprises the first active columns or the second active columns which are intersected with the third direction and are perpendicular to the first direction; a word line surrounding the first active pillar and the second active pillar; A first memory structure located on a first side of the active pillar array and electrically connected to the first active region of the first active pillar; A second storage structure located on a second side of the active pillar array and electrically connected with a second active region of the second active pillar; the first side and the second side are two opposite sides of the active pillar array along the first direction; a first bit line located on a second side of the active pillar array and connected to a second active region of the first active pillar; and the second bit line is positioned on the first side of the active column array and is connected with the first active region of the second active column.
2. 2. The semiconductor structure of claim 1, wherein the word line extends along the second direction and surrounds the first active pillars and the second active pillars of the same row arranged along the second direction.
3. 3. The semiconductor structure of claim 1, wherein the first active pillars are offset from the first storage structures in the second direction at a geometric center of the first planar projection, and/or wherein the second active pillars are offset from the second storage structures in the second direction at a geometric center of the first planar projection, and wherein the first plane is perpendicular to the first direction.
4. 4. The semiconductor structure according to claim 3, wherein the row of active pillars comprises first row of active pillars and second row of active pillars alternately arranged in the third direction, wherein among a plurality of first storage structures electrically connected with the first row of active pillars, two adjacent first storage structures are respectively C1 and C2 at the geometric center of the first plane projection, and among a plurality of first storage structures electrically connected with the second row of active pillars adjacent to the first row of active pillars, a first storage structure with the smallest sum of distances between C1 and C2 is C3 at the geometric center of the first plane projection, and a connecting line of the C1, C2 and C3 is in an equilateral triangle; and/or the number of the groups of groups, And among the plurality of second storage structures electrically connected with the first row of active columns, the second storage structure with the smallest sum of the distances between the second storage structures and the C4 and the C5 is C6 in the geometric center of the first plane projection, and the connecting line of the C4, the C5 and the C6 is in an equilateral triangle.
5. 5. The semiconductor structure of claim 1, wherein the first bit line and the second bit line each extend along the third direction; The first bit line is connected with the second active areas of the first active columns of the same column arranged along the third direction; The second bit lines are connected to the first active regions of the second active pillars of the same column arranged along the third direction.
6. 6. The semiconductor structure of claim 1, further comprising a gate oxide layer surrounding the first active pillars and the second active pillars, the word line surrounding the gate oxide layer.
7. 7. The semiconductor structure of claim 1, wherein the first bit line is located between the active pillar array and the second memory structure, and the second bit line is located between the active pillar array and the first memory structure.
8. 8. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises: a first contact structure located between the array of active pillars and the first storage structure for electrically connecting a first active region of the first active pillar with the first storage structure; And the second contact structure is positioned between the active column array and the second storage structure and is used for electrically connecting the second active region of the second active column with the second storage structure.
9. 9. The semiconductor structure of claim 1, wherein the semiconductor structure comprises a dynamic random access memory, and wherein the first memory structure and the second memory structure each comprise a storage capacitor.
10. 10. A memory system, comprising: A semiconductor structure as claimed in any one of claims 1 to 9, and A memory controller coupled with and controlling the semiconductor structure.
11. 11. A method of fabricating a semiconductor structure, the method comprising: Forming an active column array, wherein the active column array comprises a first active column and a second active column which are arranged in an array manner, each of the first active column and the second active column comprises a channel region, a first active region and a second active region which are respectively positioned at two opposite ends of the channel region along a first direction, the first direction is the extending direction of the channel region, the first active column and the second active column form a plurality of columns of active columns which are arranged along a second direction and a plurality of rows of active columns which are arranged along a third direction, each column of active columns comprises the first active columns and the second active columns which are alternately arranged, and each column of active columns comprises the first active columns or the second active columns which are intersected with the third direction and are perpendicular to the first direction; Forming a word line surrounding the first active pillars and the second active pillars; Forming a second bit line and a first storage structure on a first side of the active column array respectively, wherein the second bit line is connected with a first active region of the second active column, and the first storage structure is electrically connected with the first active region of the first active column; And forming a first bit line and a second memory structure on a second side of the active column array respectively, wherein the first bit line is connected with a second active region of the first active column, the second memory structure is electrically connected with a second active region of the second active column, and the first side and the second side are two opposite sides of the active column array along the first direction.
12. 12. The method of manufacturing of claim 11, wherein the word line extends along the second direction and surrounds the first active pillars and the second active pillars of the same row arranged along the second direction.
13. 13. The method of claim 11, wherein the first active pillars are offset from the first storage structures in the second direction from the geometric centers of the first planar projections, and/or the second active pillars are offset from the second storage structures in the second direction from the geometric centers of the first planar projections, and wherein the first plane is perpendicular to the first direction.
14. 14. The manufacturing method of claim 13, wherein the row of active pillars comprises first row of active pillars and second row of active pillars alternately arranged in the third direction, wherein the geometric centers of the adjacent two first storage structures in the first plane projection are C1 and C2 respectively in the first storage structures electrically connected with the first row of active pillars, the geometric center of the first storage structure in the first plane projection is C3, and the first storage structure with the smallest sum of the distances between the C1 and C2 in the first storage structures in the second row of active pillars is the geometric center of the first plane projection, and the connecting line of the C1, the C2 and the C3 is in an equilateral triangle; and/or the number of the groups of groups, And among the plurality of second storage structures electrically connected with the first row of active columns, the second storage structure with the smallest sum of the distances between the second storage structures and the C4 and the C5 is C6 in the geometric center of the first plane projection, and the connecting line of the C4, the C5 and the C6 is in an equilateral triangle.
15. 15. The method of claim 11, wherein the first bit line and the second bit line each extend along the third direction; The first bit line is connected with the second active areas of the first active columns of the same column arranged along the third direction; The second bit lines are connected to the first active regions of the second active pillars of the same column arranged along the third direction.
16. 16. The method of claim 11, further comprising forming a gate oxide layer surrounding the first active pillars and the second active pillars, the word line surrounding the gate oxide layer.
17. 17. The method of claim 11, wherein, Forming a second bit line and a first memory structure, comprising: Forming a second bit line on a first side of the active pillar array; forming a first memory structure on the second bit line; forming a first bit line and a second memory structure, comprising: Forming a first bit line on a second side of the active pillar array; A second memory structure is formed on the first bit line.
18. 18. The method of manufacturing of claim 11, further comprising: Forming a first contact structure on a first side of the active pillar array prior to forming the first memory structure, the first contact structure for electrically connecting a first active region of the first active pillar with the first memory structure; and forming a second contact structure on a second side of the active pillar array before forming the second memory structure, wherein the second contact structure is used for electrically connecting a second active region of the second active pillar with the second memory structure.

Description

Semiconductor structure, manufacturing method thereof and memory system Technical Field The disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure, a manufacturing method thereof and a memory system. Background A memory array architecture of a dynamic random access memory (DRAM, dynamic Random Access Memory) is an array of memory cells (i.e., 1T1C memory cells) that include one transistor and one capacitor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. As the size of dynamic random access memories continues to shrink, the size of transistors continues to shrink. How to form a dynamic random access memory with larger storage capacity, smaller size and higher performance is a problem to be solved. BRIEF SUMMARY OF THE PRESENT DISCLOSURE The embodiment of the disclosure provides a semiconductor structure, a manufacturing method thereof and a memory system. According to one aspect of the present disclosure, there is provided a semiconductor structure comprising: The active column array comprises first active columns and second active columns which are arranged in an array manner, wherein each of the first active columns and the second active columns comprises a channel region, and a first active region and a second active region which are respectively positioned at two opposite ends of the channel region along a first direction, and the first direction is the extending direction of the channel region; a word line surrounding the first active pillar and the second active pillar; A first memory structure located on a first side of the active pillar array and electrically connected to the first active region of the first active pillar; A second storage structure located on a second side of the active pillar array and electrically connected with a second active region of the second active pillar; the first side and the second side are two opposite sides of the active pillar array along the first direction; a first bit line located on a second side of the active pillar array and connected to a second active region of the first active pillar; and the second bit line is positioned on the first side of the active column array and is connected with the first active region of the second active column. In the above scheme, the first active columns and the second active columns form a plurality of columns of active columns arranged along a second direction and a plurality of rows of active columns arranged along a third direction, each row of active columns comprises the first active columns and the second active columns which are alternately arranged, each column of active columns comprises the first active columns or the second active columns, and the second direction intersects with the third direction and is perpendicular to the first direction. In the above scheme, the word line extends along the second direction and surrounds the first active pillars and the second active pillars of the same row arranged along the second direction. In the scheme, the geometric center of the first active column projected on the first plane and the geometric center of the first storage structure projected on the first plane are offset along the second direction, and/or the geometric center of the second active column projected on the first plane and the geometric center of the second storage structure projected on the first plane are offset along the second direction, and the first plane is perpendicular to the first direction. In the scheme, the row of active columns comprises first row of active columns and second row of active columns which are alternately arranged in the third direction, wherein the geometric centers of the adjacent two first storage structures projected on the first plane are C1 and C2 respectively in a plurality of first storage structures electrically connected with the first row of active columns, the geometric center of the first storage structure projected on the first plane is C3, and the first storage structure with the smallest sum of the distances between the adjacent two first storage structures and the adjacent second row of active columns is C1 and C2, and the connecting line of the adjacent two first storage structures and the adjacent second storage structure is an equilateral triangle; and/or the number of the groups of groups, And among the plurality of second storage structures electrically connected with the first row of active columns, the second storage structure with the smallest sum of the distances between the second storage structures and the C4 and the C5 is C6 in the geometric center of the first plane projection, and the connecting line of the C4, the C5 and the C6 is in an equilateral triangle. In the above aspect, the first bit line and the second bit line extend along the third direction; The first bit line is connected with the second acti