CN-116338430-B - Performance test method for CAF resistance of high-multilayer board adjacent conductor

CN116338430BCN 116338430 BCN116338430 BCN 116338430BCN-116338430-B

Abstract

The invention relates to the technical field of circuit boards, and discloses a performance test method for CAF (computer aided design) resistance of a high-multilayer-board adjacent conductor, which is used for improving accuracy and efficiency when the CAF resistance test is carried out on a PCB (printed circuit board). The method comprises the steps of carrying out target layer analysis on a target high-multilayer board, determining a first target layer and a second target layer, setting a first test pattern on the first target layer, setting a second test pattern on the second target layer, carrying out hole site analysis on the first test pattern and the second test pattern, determining hole site information, carrying out hole site information on the target high-multilayer board, carrying out hole site processing on the target high-multilayer board to obtain a plurality of holes, setting a third test pattern on the second target layer based on the plurality of holes, simultaneously connecting a test pad with the third test pattern, carrying out resistance value detection on the third test pattern through a four-wire micro-resistance tester, determining a plurality of resistance values, carrying out CAF resistance analysis on the target high-multilayer board, and determining a performance analysis result.

Inventors

GENG BO
WANG YUE
JIAO PENGYUN

Assignees

天津普林电路股份有限公司

Dates

Publication Date: 20260505
Application Date: 20230328

Claims (5)

1. A performance test method for CAF resistance of a high multilayer board adjacent conductor is characterized by comprising the following steps: performing target layer analysis on the target high multilayer board, and determining a corresponding first target layer and a corresponding second target layer; Setting a first test pattern in a preset area of the first target layer, and setting a second test pattern in a preset area of the second target layer, wherein at least one detection line is set in the first test pattern, and at least one detection line is set in the second test pattern; performing hole site analysis through the first test pattern and the second test pattern to determine corresponding hole site information; Drilling the target high multilayer board through the hole site information, and drilling from the first target layer of the target high multilayer board to the second target layer of the target high multilayer board to obtain a plurality of drill holes; setting a third test pattern on the second target layer based on the plurality of drilling holes, and simultaneously connecting a preset test pad with the third test pattern; the step of detecting the resistance value of the third test pattern by the preset four-wire micro-resistance tester to determine a plurality of resistance values comprises the following steps: performing measurement point location analysis on the third test pattern to determine a plurality of corresponding measurement point locations; Detecting resistance values of each group of measurement points through the four-wire micro-resistance tester, and determining a plurality of resistance values; and performing CAF resistance analysis on the target high multilayer board through the plurality of resistance values, and determining a corresponding performance analysis result, wherein the step comprises the following steps: vector mapping is carried out on the plurality of resistance values respectively, and a plurality of corresponding resistance vectors are determined; performing CAF resistance analysis on the target high multilayer board through the plurality of resistance vectors, and determining corresponding performance analysis results; and the step of determining the corresponding performance analysis result by performing CAF resistance performance analysis on the target high multilayer board through the plurality of resistance vectors comprises the following steps: calculating the characteristic value of each resistance vector, and determining the characteristic value corresponding to each resistance vector; respectively carrying out threshold analysis on the characteristic values corresponding to each resistance vector, and determining a corresponding threshold analysis result; performing CAF resistance analysis on the target high multilayer board according to the threshold analysis result, and determining a corresponding performance analysis result; And carrying out CAF resistance analysis on the target high multilayer board through the plurality of resistance values, and determining a corresponding performance analysis result.
2. The method for testing the CAF resistance of the high multilayer board adjacent conductor according to claim 1, wherein the step of performing target layer analysis on the target high multilayer board to determine the corresponding first target layer and second target layer comprises the steps of: analyzing the adjacent interlayer spacing of the target high multilayer board, and determining a plurality of adjacent interlayer spacing values; performing minimum value analysis on the plurality of adjacent layer interval values to determine a corresponding interval minimum value; And carrying out target layer analysis on the target high multilayer board through the minimum distance value, and determining a corresponding first target layer and a corresponding second target layer.
3. The method for testing the CAF resistance of the high multilayer board adjacent conductor according to claim 1, wherein the step of determining the corresponding hole site information by analyzing the hole sites through the first test pattern and the second test pattern comprises the steps of: Performing first hole site analysis on at least one detection line arranged in the first test pattern to determine a first hole site set; performing second hole site analysis on at least one detection line arranged in the second test pattern to determine a second hole site set; and generating hole site information through the first hole site set and the second hole site set, and determining corresponding hole site information.
4. The method for testing the CAF performance of a high multilayer board adjacent conductor according to claim 3, wherein the step of analyzing the first hole site on at least one test line set in the first test pattern to determine the first hole site set comprises: Analyzing the end point position of at least one detection line arranged in the first test graph, and determining a corresponding end point position set; And carrying out first hole site analysis on at least one detection line arranged in the first test pattern through the end point position set to determine a first hole site set.
5. The method for testing the CAF performance of the high multilayer board adjacent conductor according to claim 1, wherein a third test pattern is set on the second target layer based on the plurality of holes, and simultaneously, a preset test pad is connected with the third test pattern, comprising: Based on the plurality of drill holes, performing test pattern setting area analysis on the second target layer, and determining a corresponding image setting area; based on the image setting area, setting a test pattern on the second target layer to generate a third test pattern; And connecting a preset test pad with the third test pattern.

Description

Performance test method for CAF resistance of high-multilayer board adjacent conductor Technical Field The invention relates to the technical field of circuit boards, in particular to a performance test method for CAF resistance of a high-multilayer board adjacent conductor. Background With the rapid development of electronic information technology, the PCB is gradually developed to be small, dense, thin and precise, the PCB wiring design is more and more dense, the aperture is more and more small, the wiring line width and line spacing of the high multilayer board and the HDI board are common at 3mil/3mil at present, and the minimum aperture is 0.15mm. Such high density routing allows for smaller and smaller pitches between different networks between PCB conductors. Typically there is a risk of CAF failure if the conductor spacing of the different networks is below 0.3 mm. At present, CAF failure is generally evaluated by using a standard test pattern, the designed conductor spacing is generally more than or equal to 0.3mm, the designed conductor spacing cannot be designed on the same product as the PCB required by actual customers, if the test pattern is used as a CAF failure evaluation means, the test time is generally 1000 hours, the short circuit problem occurs, destructive slice analysis is needed to find out the layer of the problem point, and the CAF resistance of the actual processed product cannot be evaluated in a targeted and rapid manner. And the product is sent to the customer, and if the customer stores the product for a period of time and then uses the product, the customer does not have a good method to evaluate the performance state change of the product before using the product. Disclosure of Invention In view of the above, the embodiment of the invention provides a performance test method for CAF resistance of a high multilayer board adjacent conductor, which solves the technical problems of lower accuracy and efficiency when the CAF resistance test is performed on a PCB. The invention provides a performance test method for CAF (capacitance of an adjacent conductor) performance of a high-multilayer board, which comprises the steps of carrying out target layer analysis on the target high-multilayer board, determining a corresponding first target layer and a corresponding second target layer, setting a first test pattern in a preset area of the first target layer, setting a second test pattern in a preset area of the second target layer, setting at least one detection line in the first test pattern, setting at least one detection line in the second test pattern, carrying out hole site analysis on the first test pattern and the second test pattern to determine corresponding hole site information, carrying out hole site information on the target high-multilayer board, obtaining a plurality of holes from the first target layer of the target high-multilayer board until the second target layer of the target high-multilayer board is drilled, setting a third test pattern in the second target layer, simultaneously connecting a preset test pad with the third test pattern based on the plurality of holes, carrying out hole site analysis on the third test pattern through a preset four-wire micro-resistance tester, and carrying out hole site analysis on the resistance value of the third test pattern, and determining a plurality of resistance values corresponding to the performance analysis result. The method comprises the steps of carrying out target layer analysis on a target high multilayer board and determining a corresponding first target layer and a corresponding second target layer, wherein the steps comprise carrying out adjacent layer spacing analysis on the target high multilayer board and determining a plurality of adjacent layer spacing values, carrying out minimum value analysis on the plurality of adjacent layer spacing values and determining a corresponding minimum distance value, and carrying out target layer analysis on the target high multilayer board through the minimum distance value and determining a corresponding first target layer and a corresponding second target layer. The step of determining the corresponding hole site information comprises the steps of performing first hole site analysis on at least one detection line arranged in the first test pattern to determine a first hole site set, performing second hole site analysis on at least one detection line arranged in the second test pattern to determine a second hole site set, and performing hole site information generation through the first hole site set and the second hole site set to determine the corresponding hole site information. In the invention, the step of analyzing the first hole site of at least one detection line arranged in the first test pattern and determining the first hole site set comprises the steps of analyzing the end point position of at least one detection line arranged in the first test pattern and dete