CN-116364683-B - Packaging substrate structure for realizing direct interconnection between chips and manufacturing method thereof

CN116364683BCN 116364683 BCN116364683 BCN 116364683BCN-116364683-B

Abstract

The invention relates to a packaging substrate structure for realizing direct interconnection between chips, which comprises a substrate, a first dielectric layer, a first chip, a second dielectric layer, a second metal through hole, a third dielectric layer, a third metal through hole, a fourth metal through hole, a third metal through hole and a second metal through hole, wherein the first dielectric layer is arranged in the first dielectric layer in a way that the front side of the chip is upwards buried, the first chip is provided with a first bonding pad and a second bonding pad with a size larger than that of the first bonding pad, the second dielectric layer is arranged in the second dielectric layer in a way that the first metal through hole penetrates through the second dielectric layer and is electrically connected with the substrate bonding pad, the second metal through hole penetrates through the second dielectric layer and the first dielectric layer and is electrically connected with the substrate bonding pad, the third metal through hole penetrates through the third dielectric layer and the second dielectric layer and is electrically connected with the first bonding pad, the top surfaces of the third metal through hole and the fourth metal through hole are respectively provided with bonding pads, and the second chip is welded on the bonding pad on the top surfaces of the third metal through bumps in a flip-chip manner.

Inventors

ZHENG MAORONG
DING CAIHUA

Assignees

上海先方半导体有限公司
华进半导体封装先导技术研发中心有限公司

Dates

Publication Date: 20260505
Application Date: 20230314

Claims (10)

1. A package substrate structure for realizing direct interconnection between chips, comprising: a substrate, wherein the front surface of the substrate is provided with a substrate bonding pad; The first dielectric layer is arranged on the front surface of the substrate; The first chip is buried in the first dielectric layer in an upward right side, and is provided with a first bonding pad and a second bonding pad with a size larger than that of the first bonding pad; a second dielectric layer covering the first dielectric layer and the first chip; the first metal through hole penetrates through the second dielectric layer and is electrically connected with the second bonding pad of the first chip; The second metal through hole penetrates through the second dielectric layer and the first dielectric layer and is electrically connected with the substrate bonding pad; A third dielectric layer covering the second dielectric layer; A third metal through hole penetrating the third dielectric layer and the second dielectric layer and electrically connected with the first bonding pad of the first chip; a fourth metal via penetrating the third dielectric layer and electrically connected to the second metal via, wherein the top surfaces of the third and fourth metal vias and the upper surface of the third dielectric layer are provided with bonding pads, and And the second chip is flip-chip welded on the bonding pad on the top surface of the third metal through hole and the bonding pad on the upper surface of the third dielectric layer through the bumps.
2. The package substrate structure for achieving direct inter-chip interconnection of claim 1, further comprising: A first re-wiring layer disposed on the upper surface of the second dielectric layer and electrically connecting the first metal via and the second metal via, and And the second rewiring layer is arranged on the upper surface of the third dielectric layer and is electrically connected with the first metal through hole, the second metal through hole and the bonding pad on the upper surface of the third dielectric layer.
3. The package substrate structure for achieving direct inter-chip interconnection of claim 1, wherein the second chip has a first bump and a second bump having a larger size than the first bump.
4. The package substrate structure for achieving direct inter-chip interconnection of claim 3, wherein a size of the first bump is matched with a size of the third metal via, and a size of the second bump is matched with a size of a pad on an upper surface of the third dielectric layer.
5. The package substrate structure for realizing direct inter-chip interconnection as claimed in claim 3, wherein said first bump is composed of copper pillar and solder ball at head of copper pillar, and/or The second bump is a solder ball.
6. The package substrate structure for achieving direct inter-chip interconnection of claim 1, wherein the aperture of the third metal via is smaller than the aperture of the first metal via.
7. A manufacturing method of a packaging substrate structure for realizing direct interconnection between chips is characterized by comprising the following steps: Arranging a first dielectric layer on the front surface of a substrate with a substrate bonding pad, and forming a chip embedded groove in the first dielectric layer; Embedding a first chip patch into a chip embedding groove, wherein the first chip is provided with a first bonding pad and a second bonding pad with a size larger than that of the first bonding pad; arranging a second dielectric layer on the first dielectric layer and the first chip; forming a first through hole communicated with a second bonding pad of the first chip in the second dielectric layer, forming a second through hole communicated with a bonding pad of the substrate in the second dielectric layer and the first dielectric layer, carrying out metallization conductive filling on the first through hole and the second through hole to form a first metal through hole and a second metal through hole, forming bonding pads on the top surfaces of the first metal through hole and the second metal through hole, and forming a first rewiring layer electrically connected with the bonding pads on the upper surface of the second dielectric layer; a third dielectric layer is arranged on the second dielectric layer; Forming a third through hole communicated with a first bonding pad of the first chip in the third dielectric layer and the second dielectric layer, forming a fourth through hole communicated with a bonding pad on the top surface of the second metal through hole in the third dielectric layer, carrying out metallization conductive filling on the third through hole and the fourth through hole to form a third metal through hole and a fourth metal through hole, forming bonding pads on the top surfaces of the third metal through hole and the fourth metal through hole and the area to be bonded with the second chip on the upper surface of the third dielectric layer, and forming a second rewiring layer electrically connected with the bonding pads on the upper surface of the third dielectric layer; And flip-chip bonding the second chip to the bonding pad on the top surface of the third metal through hole and the bonding pad on the upper surface of the third dielectric layer.
8. The method of manufacturing a package substrate structure for implementing direct inter-chip interconnection of claim 7, wherein the second chip has a first bump and a second bump having a size larger than the first bump, the size of the first bump is matched with the size of the third metal via, and the size of the second bump is matched with the size of the bonding pad on the upper surface of the third dielectric layer.
9. The method of manufacturing a package substrate structure for direct inter-chip interconnection as claimed in claim 8, wherein the first bump is composed of a copper pillar and a solder ball at a head of the copper pillar, and/or The second bump is a solder ball.
10. The method of manufacturing a package substrate structure for achieving direct inter-chip interconnection of claim 7, wherein the aperture of the third metal via is smaller than the aperture of the first metal via.

Description

Packaging substrate structure for realizing direct interconnection between chips and manufacturing method thereof Technical Field The invention relates to the technical field of semiconductor packaging, in particular to a packaging substrate structure for realizing direct interconnection between chips and a manufacturing method thereof. Background In the conventional packaging technology, in order to realize interconnection communication between chips, the interconnection communication between chips is generally realized through wiring of a packaging substrate or rewiring of an interposer (a silicon interposer, etc.). On the one hand, with the rapid development of artificial intelligence technology, 5G technology, portable mobile communication devices, etc., the I/O density of semiconductor devices such as CPU, GPU, HBM and FPGAs has been drastically increased, and Pad Pitch has been reduced, so that conventional organic package substrates have been insufficient to support the above-mentioned high-density interconnection between chips. On the other hand, in the technology of silicon Interposer (Si-Interposer), since the wiring on the Si-Interposer can realize the line width and the line spacing of micron and submicron level, the requirement of high density interconnection among a plurality of heterogeneous chips can be satisfied. The technological process of the Si-Interposer includes making TSV (Through Silicon Via) and RDLs (Redistribution Layer) on the Si-Interposer, mounting multiple chips on the Si-Interposer in Flip-Chip mode, and mounting the Si-Interposer with chips on Substrate to complete the interconnection communication between chips and Substrate. However, the process is complex, the cost is high, and the yield of the TSV with high aspect ratio is low, which is a main impediment factor for large-scale popularization of the TSV technology. In addition, the inter-chip interconnection communication is performed by substrate routing or by interposer rerouting, which may result in signal delay and loss due to the added inter-chip trace length. Therefore, how to realize high-density and low-loss interconnection between chips without an interposer and without re-wiring is a big problem to be solved. Disclosure of Invention To solve at least some of the above problems in the prior art, the present invention provides a package substrate structure for realizing direct interconnection between chips, comprising: a substrate, wherein the front surface of the substrate is provided with a substrate bonding pad; The first dielectric layer is arranged on the front surface of the substrate; The first chip is buried in the first dielectric layer in an upward right side, and is provided with a first bonding pad and a second bonding pad with a size larger than that of the first bonding pad; a second dielectric layer covering the first dielectric layer and the first chip; the first metal through hole penetrates through the second dielectric layer and is electrically connected with the second bonding pad of the first chip; The second metal through hole penetrates through the second dielectric layer and the first dielectric layer and is electrically connected with the substrate bonding pad; A third dielectric layer covering the second dielectric layer; A third metal through hole penetrating the third dielectric layer and the second dielectric layer and electrically connected with the first bonding pad of the first chip; a fourth metal via penetrating the third dielectric layer and electrically connected to the second metal via, wherein the top surfaces of the third and fourth metal vias and the upper surface of the third dielectric layer are provided with bonding pads, and And the second chip is flip-chip welded on the bonding pad on the top surface of the third metal through hole and the bonding pad on the upper surface of the third dielectric layer through the bumps. Further, the method further comprises the following steps: A first re-wiring layer disposed on the upper surface of the second dielectric layer and electrically connecting the first metal via and the second metal via, and And the second rewiring layer is arranged on the upper surface of the third dielectric layer and is electrically connected with the first metal through hole and the second metal through hole. Further, the second chip has a first bump and a second bump having a size larger than the first bump. Further, the size of the first bump is matched with the size of the third metal through hole, and the size of the second bump is matched with the size of a bonding pad on the upper surface of the third dielectric layer. Further, the first bump is composed of a copper pillar and a solder ball positioned at the head of the copper pillar, and/or The second bump is a solder ball. Further, the aperture of the third metal through hole is smaller than that of the first metal through hole. The invention also provides a manufacturing method of the packagin