CN-116403890-B - Packaging method
Abstract
A packaging method comprises the steps of providing a first wafer, carrying out multiple wafer stacking operations, wherein the wafer stacking operations comprise forming a first wafer to be bonded in a boss shape and comprising a base part and a boss protruding from the base part, enabling the boss to face a second wafer to be bonded and be bonded with the second wafer to be bonded to form a stacked wafer, carrying out thinning treatment on the back surface of the first wafer to be bonded, wherein the thickness of the thinning treatment is at least equal to that of the first base part, forming a first dielectric layer on the surface of the boss, enabling the corner of the first dielectric layer to be arc-shaped, carrying out second trimming treatment on the edge area of the boss and the edge area of the second wafer to be bonded, enabling the remaining second wafer to be bonded after the second trimming treatment to be in the boss shape, and enabling the remaining stacked wafer after the second trimming treatment to be used as the first wafer to be bonded after the subsequent wafer stacking treatment. The probability of residues left on the surface of the second wafer to be bonded is reduced, so that the performance of the semiconductor structure can be improved.
Inventors
- LIU QINGZHAO
- YAN DAYONG
- ZHAO YAJUN
- LIU MIN
- WANG YANG
Assignees
- 中芯国际集成电路制造(上海)有限公司
- 中芯国际集成电路制造(北京)有限公司
Dates
- Publication Date
- 20260512
- Application Date
- 20211223
Claims (11)
- 1. A method of packaging, comprising: Providing a first wafer; performing a plurality of wafer stacking operations, the wafer stacking operations comprising: Forming a first wafer to be bonded in a boss shape, wherein the first wafer to be bonded comprises a base part and a protruding part protruding out of the base part, and the forming of the first wafer to be bonded comprises the steps of carrying out first trimming treatment on an edge area of the front surface of the first wafer, wherein the first wafer remained after the first trimming treatment is used as the first wafer to be bonded; the convex part faces to a second wafer to be bonded and is bonded with the second wafer to be bonded to form a stacked wafer; After bonding, thinning the back surface of the first wafer to be bonded, wherein the thickness of the thinning is at least the thickness of the base part; After the thinning treatment, forming a first dielectric layer on the surface of the protruding part, wherein the corner of the first dielectric layer is arc-shaped; And after the first dielectric layer is formed, performing second trimming treatment on the edge area of the protruding part and the edge area of the second wafer to be bonded, so that the remaining second wafer to be bonded after the second trimming treatment is in a boss shape, and the remaining stacked wafer after the second trimming treatment is used as the first wafer to be bonded for the next wafer stacking treatment.
- 2. The packaging method of claim 1, wherein the wafer stacking operation further comprises forming a second dielectric layer on sidewalls of the bump after the second trimming process.
- 3. The packaging method of claim 2, wherein the wafer stacking operation further comprises planarizing the first dielectric layer on top of the bump after the second trimming process before forming the second dielectric layer; In the step of forming the second dielectric layer, the second dielectric layer is formed on the top and the side wall of the protruding portion and the top of the second wafer to be bonded.
- 4. The packaging method of claim 1, wherein the process of forming the first dielectric layer comprises an atomic layer deposition process or a chemical vapor deposition process.
- 5. The packaging method of claim 2, wherein the process of forming the second dielectric layer comprises an atomic layer deposition process or a chemical vapor deposition process.
- 6. The method of packaging of claim 1, wherein in the step of forming the first dielectric layer, the material of the first dielectric layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.
- 7. The method of packaging of claim 2, wherein in the step of forming the second dielectric layer, the material of the second dielectric layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.
- 8. The packaging method of claim 1, wherein in the step of forming the first dielectric layer, a thickness of the first dielectric layer is 500 nm to 2900 nm.
- 9. The packaging method of claim 2, wherein in the step of forming the second dielectric layer, a thickness of the second dielectric layer is 50 nm to 100 nm.
- 10. The packaging method of claim 1, wherein the first trimming process and the second trimming process are performed using a blade.
- 11. The packaging method of claim 1, wherein the parameters of the second trimming process each include a trimming depth in the range of 20 microns to 200 microns and a trimming width in the range of 0.5 microns to 5 microns.
Description
Packaging method Technical Field The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a packaging method. Background In some existing semiconductor processes, such as 3D-IC wafer bonding and subsequent wafer thinning processes, trimming (Trim) of the wafer is required to ensure the integrity and smoothness of the wafer edge. One of the wafers needs to be trimmed for the first time before bonding the two adjacent wafers, then bonding the two adjacent wafers, grinding and thinning the wafer on the top layer, and then adopting a second trimming process to obtain an ideal edge. In the multi-wafer stacking process, the previous steps are repeated. Disclosure of Invention The embodiment of the invention solves the problem of providing a packaging method for improving the performance of a semiconductor structure. In order to solve the problems, the embodiment of the invention provides a packaging method, which comprises the steps of providing a first wafer, conducting a plurality of wafer stacking operations, wherein the wafer stacking operations comprise forming a first wafer to be bonded in a boss shape and comprising a base part and a protruding part protruding out of the base part, the forming of the first wafer to be bonded comprises the steps of conducting first trimming treatment on the edge area of the front surface of the first wafer, enabling the remaining first wafer after the first trimming treatment to serve as the first wafer to be bonded, enabling the protruding part to face a second wafer to be bonded, conducting thinning treatment on the back surface of the first wafer to be bonded after bonding, enabling the thickness of the thinning treatment to be at least the thickness of the first base part, conducting arc-shaped at the corner of the first dielectric layer, enabling the protruding part to face the second wafer to be bonded, enabling the remaining edge of the second wafer to be subjected to be trimmed after the first trimming treatment to be conducted, enabling the protruding part to be in the shape to serve as the protruding part, enabling the remaining second wafer to be subjected to be bonded, and enabling the protruding part to be subjected to first trimming treatment to be in the first bonding treatment, and enabling the remaining edge area to be subjected to the second wafer to be subjected to first bonding treatment to be subjected to the first bonding treatment. Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages: The embodiment of the invention provides a packaging method, which is used for carrying out a plurality of wafer stacking operations, wherein the wafer stacking operations comprise the steps of enabling a protruding part to face a second wafer to be bonded and bonding the protruding part and the second wafer to be bonded to form a stacked wafer, carrying out thinning treatment on the back surface of a first wafer to be bonded after bonding, wherein the thickness of the thinning treatment is at least equal to that of a first base part, forming a first dielectric layer on the surface of the protruding part after thinning treatment, and enabling corners of the first dielectric layer to be arc-shaped, and in the process of carrying out second trimming treatment, the corners of the first dielectric layer are arc-shaped, and the first dielectric layer is tightly attached to the surface of the protruding part and the surface of the second wafer to be bonded, so that damage to tools adopted by the second trimming treatment is reduced, correspondingly, the probability of residues remaining on the surface of the second wafer to be bonded is reduced in the subsequent thinning treatment process, and accordingly, the performance of the semiconductor structure can be improved. Drawings Fig. 1 to 5 are schematic structural diagrams corresponding to each step in a packaging method; Fig. 6 to 13 are schematic structural diagrams corresponding to each step in an embodiment of the packaging method of the present invention. Detailed Description The performance of current semiconductor structures is to be improved. The reasons why the performance is to be improved are now analyzed in combination with a packaging method. Fig. 1 to 5 are schematic structural diagrams corresponding to each step in a packaging method. Referring to fig. 1, a first wafer 10 is provided. Referring to fig. 2, the first wafer 10 is subjected to a first trimming process to form a first wafer 13 to be bonded in a boss shape, and the first wafer 13 to be bonded includes a base portion 11 and a protruding portion 12 protruding from the base portion 11. Referring to fig. 3, the bump 12 faces the second wafer to be bonded 15, and bonding is achieved between the first wafer to be bonded 13 and the second wafer to be bonded 15 through the bonding layer 16. Referring to fig. 4, after bonding, the back surface of the first