CN-116414454-B - Vector instruction processing method and device based on RISC-V instruction set and readable storage medium

CN116414454BCN 116414454 BCN116414454 BCN 116414454BCN-116414454-B

Abstract

The embodiment of the invention discloses a vector instruction processing method, a vector instruction processing device and a readable storage medium based on a RISC-V instruction set. The embodiment of the invention executes a configuration instruction to acquire configuration parameters of the configuration instruction, updates the acquired configuration parameters into a file entry corresponding to the configuration instruction according to a tag index, sets a destination register in the file entry as a preparation state, sets the destination register of the configuration instruction as a first source register of a vector instruction corresponding to the configuration instruction, responds to the first source register and other source registers of the vector instruction as preparation states, acquires the configuration parameters in the file entry according to the tag index carried in the vector instruction, and executes the vector instruction. By the method, under the condition that the vector instructions are executed out of order, the configuration parameters Vtype and Vl of the corresponding configuration instructions can be accurately obtained according to the tag index, and the accuracy of processing results when the vector processor processes the vector instructions is guaranteed.

Inventors

HU KUN
OUYANG XIN
ZHANG KENING

Assignees

北京希姆计算科技有限公司

Dates

Publication Date: 20260505
Application Date: 20211230

Claims (10)

1. A vector instruction processing method based on RISC-V instruction set, the method comprising: executing a configuration instruction, and acquiring configuration parameters of the configuration instruction, wherein the configuration instruction carries a tag index; Updating the acquired configuration parameters to file entries corresponding to the configuration instructions according to the tag indexes, and setting a destination register in the file entries to be in a ready state, wherein the destination register of the configuration instructions is set as a first source register of vector instructions corresponding to the configuration instructions; Responding to the preparation state of the first source register and other source registers of the vector instruction, and acquiring configuration parameters in the file entries according to tag indexes carried in the vector instruction, wherein the tag indexes carried in the vector instruction are the same as the tag indexes carried in the configuration instruction; The vector instruction is executed.
2. The method of claim 1, wherein the file entry further includes a validity indication, and wherein after updating the obtained configuration parameter to the file entry corresponding to the configuration instruction according to the tag index, the method further includes: and marking the validity indication in the file entry as valid, wherein the validity indication is used for indicating whether the configuration parameters in the file entry are valid or not.
3. The method of claim 1, wherein the method further comprises: Acquiring instruction data; In the decoding stage, responding to the instruction data as the configuration instruction, distributing corresponding file entries for the configuration instruction in a configuration cache, and generating a tag index; The tag index is added to the configuration instruction.
4. A method as claimed in claim 3, characterized in that the method further comprises: And writing a destination register of the configuration instruction into the file entry, and marking the validity indication in the file entry as invalid.
5. The method of claim 4, wherein the method further comprises: and writing the file entry corresponding to the configuration instruction into the tail part of a configuration cache.
6. The method of claim 5, wherein the method further comprises: In the decoding stage, responding to the instruction data as the vector instruction, and acquiring the file entry from the tail part of the configuration cache; In response to the validity indication in the file entry being marked invalid, adding a first source register in the file entry to a source register list of the vector instruction; A tag index in the file entry is added to the vector instruction.
7. A method as claimed in claim 3, characterized in that the method further comprises: Renaming the vector instruction and the configuration instruction after the decoding stage; And writing the vector instruction and the configuration instruction into a reorder buffer ROB after the renaming is finished, and distributing the vector instruction and the configuration instruction into different instruction slots according to different instruction types.
8. A vector instruction processing apparatus based on a RISC-V instruction set, the apparatus comprising: The first execution unit is used for executing a configuration instruction and obtaining configuration parameters of the configuration instruction, wherein the configuration instruction carries a tag index; The setting unit is used for updating the acquired configuration parameters into file entries corresponding to the configuration instructions according to the tag indexes, and setting destination registers in the file entries to be in a ready state, wherein the destination registers of the configuration instructions are set as first source registers of vector instructions corresponding to the configuration instructions; The processing unit is used for responding to the preparation state of the first source register and other source registers of the vector instruction and acquiring configuration parameters in the file entry according to the tag index carried in the vector instruction, wherein the tag index carried in the vector instruction is the same as the tag index carried in the configuration instruction; And the second execution unit is used for executing the vector instruction.
9. Computer program instructions, characterized in that it implements the method according to any of claims 1-7 when executed by a processor.
10. A computer readable storage medium, on which computer program instructions are stored, which computer program instructions, when executed by a processor, implement the method of any of claims 1-7.

Description

Vector instruction processing method and device based on RISC-V instruction set and readable storage medium Technical Field The invention relates to the technical field of computers, in particular to a vector instruction processing method and device based on a RISC-V instruction set and a readable storage medium. Background The fifth generation of reduced instruction set computer RISC-V (Reduced Instruction Set Computer-FIVE) combines the advantages of the x86 and ARM instruction sets, and has the advantages of simple instruction, less instruction number, small code and low power consumption in RISC-V, so that the application range of RISC-V is wider and wider. RISC-V comprises an existing basic instruction set and an extended instruction set, wherein the basic instruction set comprises RV32I, RV32E, RV64I and RV128I, the extended instruction set comprises M, A, F, D, C and V extensions, the V extensions are Vector extended instruction sets (RISC-V vectors), the RISC-V is realized by a Vector processor, the Vector extended instruction sets comprise configuration (Vset) instructions and Vector (Vector) instructions, the Vset instructions are Vtype and Vl parameters required by the Vector instruction configuration execution, and the execution of each Vector instruction is dependent on the configuration result of the corresponding Vset instruction. In the prior art, the Vector instructions are sequentially executed, that is, the Vector instructions can be executed only when the Vector instructions determine that the Vector instructions must be submitted, but when the Vector instructions are sequentially executed, the next Vector instruction must be executed after the execution of the previous Vector instruction is completed, and for the Vector instructions which do not depend on the execution result of the previous Vector instruction, long waiting time is also required to influence the performance of the Vector processor, so that the Vector instructions which do not depend on the execution result of the previous Vector instruction can be executed in advance, and the performance of the Vector processor is improved. However, when the Vector instruction is executed out-of-order, the corresponding Vset instruction may be executed out-of-order, and the obtained configuration parameters Vtype and Vl of the Vector instruction following the Vset instruction may be incorrect, which is the configuration parameters of other Vset instructions. In summary, how to ensure that the configuration parameters Vtype and Vl of the corresponding Vset instruction are accurately obtained under the condition that the Vector instruction is executed out of order is a problem to be solved at present. Disclosure of Invention In view of this, the embodiments of the present invention provide a Vector instruction processing method, apparatus and readable storage medium based on a RISC-V instruction set, which can ensure that, in the case of out-of-order execution of Vector instructions, configuration parameters Vtype and Vl of the corresponding Vset instruction are accurately acquired, thereby ensuring accuracy of the processing result of the Vector processor. In a first aspect, an embodiment of the present invention provides a vector instruction processing method based on a RISC-V instruction set, the method including: The method comprises the steps of executing a configuration instruction, obtaining configuration parameters of the configuration instruction, carrying a tag index in the configuration instruction, updating the obtained configuration parameters to a file entry corresponding to the configuration instruction according to the tag index, setting a destination register in the file entry to a preparation state, setting the destination register of the configuration instruction to be a first source register of a vector instruction corresponding to the configuration instruction, responding to the first source register and other source registers of the vector instruction to be preparation states, obtaining the configuration parameters in the file entry according to the tag index carried in the vector instruction, wherein the tag index carried in the vector instruction is identical to the tag index carried in the configuration instruction, and executing the vector instruction. Optionally, the file entry further includes a validity indication, and after updating the obtained configuration parameter to the file entry corresponding to the configuration instruction according to the tag index, the method further includes: and marking the validity indication in the file entry as valid, wherein the validity indication is used for indicating whether the configuration parameters in the file entry are valid or not. Optionally, the method further comprises: Acquiring instruction data; In the decoding stage, responding to the instruction data as the configuration instruction, distributing corresponding file entries for the configuration instruction