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CN-116416931-B - Display device

CN116416931BCN 116416931 BCN116416931 BCN 116416931BCN-116416931-B

Abstract

A display device includes a substrate including a display region and a non-display region surrounding the display region, a plurality of pixels disposed in the display region, a gate driver disposed at least one side of the display region in the non-display region, the gate driver including a plurality of stages including a first stage and a second stage, and a plurality of gate lines extending from the gate driver to the display region, wherein the plurality of gate lines include a first gate line including a linear portion and connected to the first stage and a second gate line including a linear portion and a curved portion and connected to the second stage, wherein a size of the second stage may be greater than a size of the first stage.

Inventors

  • Yu Shenghuan
  • LI TINGGUI

Assignees

  • 乐金显示有限公司

Dates

Publication Date
20260512
Application Date
20220822
Priority Date
20211229

Claims (15)

  1. 1. A display device, comprising: A substrate including a display region and a non-display region surrounding the display region; a plurality of pixels disposed in the display area; A gate driver disposed in the non-display region at least one side of the display region, the gate driver including a plurality of stages including a first stage and a second stage, and A plurality of gate lines extending from the gate driver to the display region, Wherein the plurality of gate lines includes a first gate line including a linear portion and connected to the first stage and a second gate line including a linear portion and a curved portion and connected to the second stage, Wherein the first stage includes a first scan buffer transistor and a first additional scan circuit adjacent to and coupled to the first scan buffer transistor, and the second stage includes a second scan buffer transistor and a second additional scan circuit adjacent to and coupled to the second scan buffer transistor, Wherein the second stage has a size greater than the first stage, an Wherein the first additional scanning circuit and the second additional scanning circuit have the same area as viewed in a plan view.
  2. 2. The display device of claim 1, wherein the size of the second stage and the size of the first stage refer to areas viewed from a plan view.
  3. 3. The display device of claim 1, wherein the display area includes a plurality of corner areas, and the second stage is disposed in a non-display area corresponding to the plurality of corner areas.
  4. 4. The display device according to claim 3, wherein the display region includes a first display region, and a second display region and a third display region extending from a portion of the first display region, a portion of the non-display region is disposed between the second display region and the third display region, and a portion of the second gate line is disposed in the second display region and the third display region.
  5. 5. The display device of claim 4, wherein the second display region and the third display region correspond to some of the plurality of corner regions, and the second stage is disposed in a non-display region corresponding to the second display region and the third display region.
  6. 6. The display device according to claim 4, wherein each of a boundary between the second display region and the non-display region and a boundary between the third display region and the non-display region includes a curved shape, and wherein a curved portion of the second gate line is disposed along the boundary between the second display region and the non-display region and the boundary between the third display region and the non-display region.
  7. 7. The display device according to claim 3, wherein the display device further comprises: A camera region located in the display region, Wherein the second gate line is disposed in the display region and located at one or more sides of the camera region.
  8. 8. The display device of claim 7, wherein the camera region corresponds to some of the plurality of corner regions, and the second stage is disposed in a non-display region corresponding to the camera region.
  9. 9. The display device of claim 1, wherein a size of the second scan buffer transistor is larger than a size of the first scan buffer transistor.
  10. 10. The display device of claim 9, wherein the plurality of stages further comprises a third stage, Wherein the first stage and the second stage output signals, and Wherein the third stage includes a dummy stage that does not output a signal, and the third stage is a preceding stage or a following stage of the second stage.
  11. 11. The display device of claim 10, wherein the third stage has a size smaller than the size of the first stage and the size of the second stage.
  12. 12. The display device of claim 11, wherein a size of a third scan buffer transistor of the third stage is smaller than a size of the first scan buffer transistor and a size of the second scan buffer transistor.
  13. 13. The display device of claim 10, wherein a spacing between the second stage and a preceding stage of the second stage is different from a spacing between the second stage and a following stage of the second stage.
  14. 14. The display device of claim 10, wherein the gate driver includes a scan driver including first, second, and third scan stages corresponding to the first, second, and third stages, respectively, and a size of the second scan stage is greater than a size of the first scan stage.
  15. 15. The display device of claim 14, wherein the first, second, and third scan stages have the first, second, and third scan buffer transistors, respectively, and the second scan buffer transistor has a size that is larger than a size of the first scan buffer transistor.

Description

Display device Cross Reference to Related Applications The present application claims the benefits and priorities of korean patent application No.10-2021-0191553 filed at the korean intellectual property office on month 29 of 2021, the disclosure of which is incorporated herein by reference. Technical Field The present disclosure relates to a display device, and more particularly, to a display device capable of reducing or minimizing RC (resistance-capacitance) delay of a gate signal. Background Currently, as the general information age is entered, the field of display devices that visually present an electric information signal has been rapidly developed, and researches are being continuously conducted to improve the performance of various display devices such as thin thickness, light weight, and low power consumption. Representative display devices may include liquid crystal display devices (LCDs), field emission display devices (FEDs), electrowetting display devices (EWDs), organic light emitting display devices (OLEDs), and the like. Among these display devices, an electroluminescent display device including an organic light emitting display device is a self-luminous display device, so that a separate light source is not required, unlike a liquid crystal display device. Accordingly, the electroluminescent display device can be manufactured to have a light weight and a small thickness. Further, since the electroluminescent display device has advantages not only in power consumption due to low voltage driving but also in color realization, response speed, viewing angle, contrast (CR), it is expected to be used in various fields. However, in a display device such as an electroluminescent display device, there is room for improvement in minimizing RC delay of a gate signal, for example. Disclosure of Invention An object to be achieved by the present disclosure is to provide a display device that can minimize RC delay variation due to a difference in length of gate lines. Another object to be achieved by the present disclosure is to provide a display device that can mitigate RC delay of a scan signal in a gate line having a curved portion to improve a flare (spot) generated in an image. The objects of the present disclosure are not limited to the above objects, and other objects not mentioned above may be clearly understood by those skilled in the art from the following description. A display device according to an aspect of the present disclosure includes a substrate including a display region and a non-display region surrounding the display region, a plurality of pixels disposed in the display region, a gate driver disposed at one or both sides of the display region in the non-display region, the gate driver including a plurality of stages including a first stage and a second stage, and a plurality of gate lines extending from the gate driver to the display region, wherein the plurality of gate lines include a first gate line including a linear portion and a second gate line including a curved portion and connected to the first stage, and the second gate line includes a linear portion and a curved portion and is connected to the second stage, wherein a size of the second stage may be greater than a size of the first stage. Additional details of exemplary embodiments are included in the following detailed description and accompanying drawings. According to the present disclosure, the RC delay variation between the gate line having only the linear portion and the gate line having the linear portion and the curved portion can be reduced. According to the present disclosure, the sampling time of the scanning signal is sufficiently ensured to improve the problem of generating a flare in an image. Effects according to the present disclosure are not limited to the above-exemplified ones, and more various effects are included in the present specification. Drawings The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description given in conjunction with the accompanying drawings in which: Fig. 1 is a schematic plan view of a display device according to an exemplary embodiment of the present disclosure; FIG. 2 is a schematic enlarged cross-sectional view taken along line II-II' of FIG. 1; Fig. 3A is a schematic diagram of a gate driver of a display device according to an exemplary embodiment of the present disclosure; FIG. 3B is a schematic diagram of a plurality of scan stages of a scan driver of a gate driver of a display device according to an exemplary embodiment of the present disclosure; fig. 4 is a schematic enlarged view of a non-display area on the right side of a display area of a display device according to an exemplary embodiment of the present disclosure; FIG. 5 is an enlarged view of area A of FIG. 1; Fig. 6 is a schematic enlarged view of corner (corner) regions of a display region and a non-display region of