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CN-116420093-B - Frequency modulated continuous wave radar system with interference mitigation

CN116420093BCN 116420093 BCN116420093 BCN 116420093BCN-116420093-B

Abstract

A method (600) for dithering a radar frame includes determining at least one of a chirp period Tc (615) of a radar chirp in the radar frame and a chirp slope S (625) of the radar chirp in the radar frame. In response to determining the chirp period Tc, a maximum chirp jitter Δc (max) is determined (620), and a random chirp jitter Δc (N) between negative Δc (max) and positive Δc (max) is determined (640) for the radar frame N. In response to determining the chirp slope S, a maximum slope jitter ψ (max) is determined (630), and for radar frame N, a random slope jitter ψ (N) between negative ψ (max) and positive ψ (max) is determined (645). The radar sensor circuit generates a radar chirp in a radar frame N based on at least one of (1) a chirp period Tc and a random chirp jitter deltac (N) and (2) a chirp slope S and a random slope jitter ψ (N) (650).

Inventors

  • S. Rao
  • A. Dabak

Assignees

  • 德克萨斯仪器股份有限公司

Dates

Publication Date
20260512
Application Date
20211018
Priority Date
20201016

Claims (20)

  1. 1. A non-transitory computer-readable storage device storing machine instructions that, when executed by one or more processors, cause the one or more processors to: determining a chirp period Tc of a radar chirp in a radar frame; Determining a maximum chirp jitter deltac (max); Determining a chirp rate S of the radar chirp in the radar frame; Determining a maximum slope jitter ψ (max); for radar frame N, at least one of the following is determined: a random chirp jitter Δc (N) between negative Δc (max) and positive Δc (max), and A random slope jitter ψ (N) between a negative ψ (max) and a positive ψ (max), and Causing a radar sensor circuit to generate the radar chirp in the radar frame N based on the chirp period Tc, the chirp slope S, and at least one of the random chirp jitter Δc (N) and the random slope jitter ψ (N).
  2. 2. The storage device of claim 1, wherein the machine instructions that cause the radar sensor circuit to generate the radar chirp in the radar frame N cause the one or more processors to cause the radar sensor circuit to transmit a plurality of radar chirps having the chirp slope S plus the random slope jitter ψ (N).
  3. 3. The storage device of claim 1, wherein the machine instructions that cause the radar sensor circuit to generate the radar chirp in the radar frame N cause the one or more processors to cause the radar sensor circuit to transmit a plurality of radar chirps at intervals equal to the chirp period Tc plus the random chirp jitter Δc (N).
  4. 4. The storage device of claim 1, further comprising machine instructions that, when executed by the one or more processors, cause the one or more processors to: Determining a period TF of the radar frame; Determining a maximum frame jitter Δf (max); For the radar frame N, determining a random frame jitter ΔF (N) between a negative ΔF (max) and a positive ΔF (max), and Causing the radar sensor circuit to generate the radar frame N further based on the period TF and the random frame jitter Δf (N).
  5. 5. The storage device of claim 4, wherein the period TF of the radar frame is based on an update rate and the maximum frame jitter Δf (max) is based on a threshold deviation from the update rate.
  6. 6. The storage device of claim 4, wherein the machine instructions that cause the radar sensor circuit to generate the radar chirp in the radar frame N cause the one or more processors to cause the radar sensor circuit to transmit multiple radar chirps during the period TF plus the random frame jitter Δf (N).
  7. 7. The storage device of claim 4, further comprising machine instructions that, when executed by the one or more processors, cause the one or more processors to: for a subsequent radar frame N+1, determining a subsequent random frame jitter ΔF (N+1) between a negative ΔF (max) and a positive ΔF (max), and Causing the radar sensor circuit to generate a radar chirp in the subsequent radar frame n+1 further based on the period TF and the subsequent random frame jitter Δf (n+1).
  8. 8. The storage device of claim 7, wherein the subsequent random frame jitter Δf (n+1) is not equal to the random frame jitter Δf (N).
  9. 9. The storage device of claim 1, further comprising machine instructions that, when executed by the one or more processors, cause the one or more processors to: for a subsequent radar frame n+1, at least one of the following is determined: a subsequent random chirp jitter deltac (n+1) between negative deltac (max) and positive deltac (max); a subsequent random slope jitter ψ (N+1) between a negative ψ (max) and a positive ψ (max), and Causing the radar sensor circuit to generate a radar chirp in the subsequent radar frame n+1 based on the chirp period Tc, the chirp slope S, and at least one of the subsequent random chirp jitter Δc (n+1) and the subsequent random slope jitter ψ (n+1).
  10. 10. The storage device of claim 9, wherein the subsequent random chirp jitter Δc (n+1) is not equal to the random chirp jitter Δc (N).
  11. 11. The memory device of claim 9, wherein the subsequent random slope jitter ψ (n+1) is not equal to the random slope jitter ψ (N).
  12. 12. The storage device of claim 1, wherein the chirp period Tc of the radar chirp is based on a threshold non-ambiguous speed and the maximum chirp jitter Δc (max) is based on a threshold deviation from the threshold non-ambiguous speed.
  13. 13. The storage device of claim 1, wherein the chirp slope S is based on a frequency range of a radar chirp in the radar frame, a threshold range resolution, and the chirp period Tc, and wherein the maximum slope jitter ψ (max) is based on a threshold deviation from the threshold range resolution.
  14. 14. An apparatus for dithering radar frames, comprising: One or more processors, and One or more non-transitory computer-readable media storing machine instructions that, when executed by the one or more processors, cause the one or more processors to: Determining at least one of a chirp period Tc of a radar chirp in a radar frame and a chirp slope S of the radar chirp in the radar frame; In response to determining the chirp period Tc: Determining a maximum chirp jitter deltac (max); For radar frame N, determining a random chirp jitter Δc (N) between negative Δc (max) and positive Δc (max); In response to determining the chirp-slope S: determining a maximum slope jitter ψ (max), and Determining a random slope jitter ψ (N) between a negative ψ (max) and a positive ψ (max) for said radar frame N, and Causing a radar sensor circuit to generate a radar chirp in the radar frame N based on at least one of (1) the chirp period Tc and the random chirp jitter Δc (N) and (2) the chirp slope S and the random slope jitter ψ (N).
  15. 15. The apparatus of claim 14, wherein the one or more non-transitory computer-readable media further comprise machine instructions that, when executed by the one or more processors, cause the one or more processors to: Determining a period TF of the radar frame; determining a maximum frame jitter DeltaF (max), and For the radar frame N, determining a random frame jitter Δf (N) between a negative Δf (max) and a positive Δf (max), wherein the machine instructions that cause the radar sensor circuit to generate the radar chirp in the radar frame N cause the one or more processors to cause the radar sensor circuit to generate the radar chirp in the radar frame N based on the period TF and the random frame jitter Δf (N).
  16. 16. The apparatus of claim 15, wherein the one or more non-transitory computer-readable media further comprise machine instructions that, when executed by the one or more processors, cause the one or more processors to: for a subsequent radar frame N+1, determining a subsequent random frame jitter ΔF (N+1) between a negative ΔF (max) and a positive ΔF (max), and Causing the radar sensor circuit to generate a radar chirp in the subsequent radar frame n+1 based on the period TF and the subsequent random frame jitter Δf (n+1).
  17. 17. The apparatus of claim 16, wherein the subsequent random frame jitter Δf (n+1) is not equal to the random frame jitter Δf (N).
  18. 18. The apparatus of claim 14, wherein the one or more non-transitory computer-readable media further comprise machine instructions that, when executed by the one or more processors, cause the one or more processors to: for a subsequent radar frame N+1, determining at least one of a subsequent random chirp jitter Δc (N+1) between negative Δc (max) and positive Δc (max) and a subsequent random slope jitter ψ (N+1) between negative ψ (max) and positive ψ (max), and Causing the radar sensor circuit to generate a radar chirp in the subsequent radar frame n+1 based on the chirp period Tc and the subsequent random chirp jitter Δc (n+1) and at least one of the chirp slope S and the subsequent random slope jitter ψ (n+1).
  19. 19. The apparatus of claim 18, wherein: the subsequent random chirp jitter Δc (n+1) is not equal to the random chirp jitter Δc (N), and The subsequent random slope jitter ψ (n+1) is not equal to the random slope jitter ψ (N).
  20. 20. The apparatus of claim 14, further comprising the radar sensor circuit.

Description

Frequency modulated continuous wave radar system with interference mitigation Technical Field Background Many driving assistance systems implement Frequency Modulated Continuous Wave (FMCW) radar systems to assist in collision warning, blind spot warning, lane change assistance, parking assistance, and rear collision warning. The fundamental transmit signal of FMCW radar is a frequency ramp, also commonly referred to as "chirp". Chirp is a signal whose frequency varies linearly with time. For example, millimeter wave radar systems may transmit chirps having a bandwidth of 4 gigahertz (GHz), starting at 77GHz and linearly increasing to 81GHz. The transmitted chirp reflects off of one or more objects and the reflected signal is received at one or more receiver antennas. FMCW radar systems transmit a series of these equidistant chirps in units called frames. The reflected signal is down-converted, digitized and then processed to obtain the range/distance (range), speed and angle of arrival of objects in front of the radar system. As radar systems become popular in automobiles, manufacturing, and other areas, the likelihood of interference between radar systems increases. One technique to reduce or mitigate radar interference is to dither intra-frame chirp timing across chirps in a radar frame. However, intra-frame chirp dithering may increase the noise floor of the radar system and reduce the detection sensitivity to weak target objects. Disclosure of Invention An apparatus includes one or more processors and one or more non-transitory computer-readable media storing machine instructions. Machine instructions, when executed by the one or more processors, cause the one or more processors to determine at least one of a chirp period Tc of a radar chirp in a radar frame and a chirp slope S of a radar chirp in a radar frame. In response to determining the chirp period Tc, the processor determines a maximum chirp jitter Δc (max) and, for the radar frame N, a random chirp jitter Δc (N) between negative Δc (max) and positive Δc (max). In response to determining the chirp-slope S, the processor determines a maximum slope jitter ψ (max) and, for a radar frame N, a random slope jitter ψ (N) between a negative ψ (max) and a positive ψ (max). The processor then causes the radar sensor circuit to generate a radar chirp in the radar frame N based on (1) the chirp period Tc and the random chirp jitter deltac (N), and (2) at least one of the chirp slope S and the random slope jitter ψ (N). In some embodiments, the apparatus further comprises a radar sensor circuit. In some embodiments, the chirp period Tc of the radar chirp is determined based on a threshold non-ambiguous speed and the maximum chirp jitter deltac (max) is based on a threshold deviation from the threshold non-ambiguous speed. In some embodiments, the chirp slope S is based on the frequency range of the radar chirp, the threshold range resolution, and the chirp period Tc, and the maximum slope jitter ψ (max) is based on the threshold deviation from the threshold range resolution. In some embodiments, the non-transitory computer readable medium further includes machine instructions that cause the processor to determine a period TF of the radar frame and a maximum frame jitter Δf (max). For radar frame N, the processor determines a random frame jitter Δf (N) between negative Δf (max) and positive Δf (max), and further generates radar frame N based on period TF and random frame jitter Δf (N). In some embodiments, the period TF of the radar frame is based on the update rate, and the maximum frame jitter Δf (max) is based on a threshold deviation from the update rate. In some implementations, the non-transitory computer-readable medium further includes machine instructions that cause the processor to determine a subsequent radar frame jitter Δf (n+1) between a negative Δf (max) and a positive Δf (max) of the subsequent radar frame n+1. The processor causes the radar sensor circuit to generate a subsequent radar frame n+1 based on the period TF and a subsequent random frame jitter Δf (n+1). In some implementations, the subsequent random frame jitter Δf (n+1) is not equal to the random frame jitter Δf (N). In some implementations, the non-transitory computer-readable medium further includes machine instructions that cause the one or more processors to determine at least one of a subsequent random chirp jitter Δc (n+1) between negative Δc (max) and positive Δc (max) and a subsequent random slope jitter ψ (N) between negative ψ (max) and positive ψ (max) for a subsequent radar frame n+1. The processor causes the radar sensor circuit to generate a radar chirp in a subsequent radar frame n+1 based on at least one of (1) a chirp period Tc and a subsequent random chirp jitter Δc (n+1) and (2) a chirp slope S and a subsequent random slope jitter ψ (n+1). In some embodiments, the subsequent random chirp jitter Δc (n+1) is not equal to the random chirp jitter Δc (N), and the su