CN-116449076-B - High-speed high-precision voltage abrupt drop monitoring circuit

CN116449076BCN 116449076 BCN116449076 BCN 116449076BCN-116449076-B

Abstract

The invention discloses a high-speed high-precision voltage abrupt drop monitoring circuit, which solves the problem that the voltage abrupt drop phenomenon in a large-scale integrated circuit is difficult to accurately and timely monitor, and belongs to the field of digital integrated circuit design and power management. The invention provides an optimization design method of a ring oscillator point circuit, which takes standard unit types, threshold values, driving capability and power consumption as variables to find the ring oscillator circuit design with highest voltage sensitivity, improves the resolution of a voltage drop monitoring circuit, provides a ring oscillator layout design which is folded once and compactly arranged, ensures load balance among nodes, provides a Nyquist counter design, counts turnover times of the nodes in a period of time, improves the voltage monitoring range, solves the problem of metastable state sampling of a traditional counter, and provides a high-speed voltage quantization circuit which carries out parallel processing on coarse quantization and fine quantization and improves the highest sampling rate and quantization rate of the voltage drop monitoring circuit.

Inventors

DU YUXUAN
QIAN JUNYI
CHEN ZHUO
SHEN ZHENGGUO
SHAN WEIWEI

Assignees

东南大学

Dates

Publication Date: 20260505
Application Date: 20230421

Claims (8)

1. A high-speed high-precision voltage drop monitoring circuit is characterized by comprising an optimally designed ring oscillator, a sampling register array, a Nyquist counter, a high-speed voltage quantization circuit and a frequency dividing circuit, wherein the optimally designed ring oscillator is utilized to map voltage changes into delay changes of standard units, the sampling register array samples the voltage state of each node of the ring oscillator according to a quantization clock F D , the counting sampling register of the Nyquist counter samples the voltage state of a counting node in n sampling clock periods, the sampling result is sent to a top-layer voltage domain, and the coarse quantization circuit of the Nyquist counter calculates the turnover number to obtain a coarse quantization result L; The ring oscillator with the optimal design is a ring oscillator circuit design which uses four dimensions of standard unit types, threshold values, driving capability and power consumption cost forming the ring oscillator as variables to find the highest voltage sensitivity, thereby improving the resolution of a voltage drop monitoring circuit; The layout optimization design method of the ring oscillator comprises the steps that the layout of the ring oscillator is designed in a one-time folding mode, standard units forming the ring oscillator are arranged on an inner layer and are divided into two rows, each row is placed at equal intervals, the distance between the two rows is the minimum distance allowed by a wiring rule, sampling registers corresponding to each standard unit are arranged on an outer layer and are placed adjacently, the fact that the wiring distances between the standard units forming the ring oscillator are equal is guaranteed, the wiring distance from the output end of each standard unit to the input end of each sampling register is minimized, and load balance among nodes of the ring oscillator is guaranteed.
2. The high-speed high-precision voltage drop monitoring circuit of claim 1, wherein the circuit design method of the ring oscillator is characterized in that the four dimensions of standard unit types, threshold values, driving capability and power consumption cost of the ring oscillator are used as variables, different node frequencies of the ring oscillator are obtained through simulation experiments, and the ring oscillator structure with larger node frequency difference has higher voltage sensitivity under fixed voltage difference.
3. The high-speed high-precision voltage drop monitoring circuit according to claim 1, wherein the ring oscillator sampling method is that the ring oscillator and the sampling register array are arranged in a tested voltage domain, the node of the ring oscillator is connected to the data end of the sampling register array, sampling is completed when each quantization clock rising edge arrives, and the sampled data is sent to a top voltage domain through a level converter to execute quantization processing.
4. The high-speed high-precision voltage drop monitoring circuit according to claim 1, wherein the nyquist counter connects a counting node on the ring oscillator to a data terminal of a counting sampling register triggered by a falling edge of the sampling clock and a data terminal of the counting sampling register triggered by a rising edge of the sampling clock, and the actual sampling rate of the nyquist counter is 2 times of the sampling clock frequency and is always higher than 2 times of the inversion frequency of the counting node, namely, the nyquist sampling law is satisfied.
5. The high-speed high-precision voltage abrupt drop monitoring circuit of a Nyquist counter is characterized in that sampling data of a counting node are sent to a top voltage domain through a level converter, two groups of shift registers are located in the top voltage domain, excitation corresponds to the counting sampling registers and are respectively a rising edge of a sampling clock and a falling edge of the sampling clock, the two groups of shift registers are used for storing the sampling data of the counting node in a period of time in a time sequence, turning occurs when adjacent data levels are different, the sampling data are achieved through exclusive OR logic, and the number of times of turning in the period of time is counted to achieve the purpose of counting.
6. The high-speed and high-precision voltage drop monitoring circuit according to claim 1, wherein the method for finely quantizing the sampling result by the high-speed voltage quantization circuit is that the sampling result of the adjacent nodes of the ring oscillator is sent to a top voltage domain to perform an exclusive OR operation to obtain a group of independent thermal codes, and the independent thermal codes are converted into binary code values, namely the turning positions of the ring oscillator at the sampling moment.
7. The high-speed high-precision voltage drop-off monitoring circuit according to claim 6, wherein the high-speed voltage quantization circuit calculates the final voltage quantization result by recording two times of fine quantization results, namely D and Dp, multiplying the two times of fine quantization results by the number of stages of the ring oscillator if D > Dp, and summing the two, subtracting 1 again from the two times of fine quantization results if D < Dp, multiplying the number of stages of the ring oscillator after subtracting 1 from the coarse quantization result, and summing the two, wherein the summation result is the change of the position of the ring oscillator in one quantization period.
8. The high-speed and high-precision voltage drop monitoring circuit according to claim 1, wherein the frequency dividing circuit is characterized in that the frequency of the quantization clock is 1/n times of the frequency of the sampling clock by a configurable register frequency dividing circuit, wherein n=2 (i-1), i is a positive integer not less than 1, and the configuration signal is SR.

Description

High-speed high-precision voltage abrupt drop monitoring circuit Technical Field The invention belongs to the field of digital integrated circuit design and power management, and particularly relates to a high-speed high-precision voltage drop monitoring circuit. Background The rapid development of integrated circuits has led to the need for processors to take on more complex and varied tasks, with severe load variations presenting challenges to the stability of the power supply network. The load change directly causes the change of the supply current, and then the voltage drop phenomenon is generated. This means that the timing margin is insufficient or even does not meet the minimum requirement, resulting in calculation errors. The voltage dip phenomenon can be generally divided into three phases, wherein the first-order voltage dip is most difficult to monitor, the frequency and the amplitude of the voltage dip depend on the package inductance and the on-chip capacitance, the frequency ranges from tens to hundreds of megahertz, and the amplitude ranges from tens to hundreds of millivolts. The traditional design can not rapidly and accurately monitor the abrupt voltage drop, so the protection ring design is adopted to cope with the abrupt voltage drop, the system is required to work at higher voltage and lower frequency, and even if the abrupt voltage drop occurs, the time sequence requirement can be met. However, the dynamic power consumption of the chip is in a quadratic relation with the voltage, and the static power consumption is in a linear relation. Therefore, the protection ring scheme may incur additional power consumption and temperature costs, against the low power design principle. In recent years, how to rapidly and accurately realize voltage drop monitoring, so that the system can make an adjustment response more quickly, further compress the protection ring to obtain energy efficiency benefits, and the system becomes a research hot spot in the current academia and industry. When the voltage drop phenomenon is faced, the traditional analog voltage drop monitoring circuit mainly realizes a threshold comparison function, and can only be used for judging whether the voltage is lower than a preset threshold or not although the analog voltage drop monitoring circuit has the advantage of simple structure. If multiple thresholds are required to be set for voltage judgment, multiple groups of reference voltages or multiple groups of voltage drop-down monitoring circuit circuits are usually required, so that hardware cost is obviously increased. On the other hand, the conventional analog-to-digital converter (analog ADC) has a low sampling frequency, and it is difficult to capture the voltage dip process. Therefore, the digital voltage drop-off monitoring circuit has the advantages of high resolution and high response speed, and is more suitable for voltage drop-off monitoring tasks than the traditional analog voltage drop-off monitoring circuit. The current digital sensor research can be mainly divided into two technical routes, namely 1) a digital voltage abrupt drop monitoring circuit constructed based on a delay chain has the advantages of simple structure and high sampling rate, but has limited monitoring range, poor stability of the delay chain and is easily influenced by noise, and 2) a voltage abrupt drop monitoring circuit constructed based on a ring oscillator has the advantages of high resolution and high sampling rate, and can monitor the voltage abrupt drop phenomenon more accurately. In addition, by combining with the design of the counter, the monitoring range of the voltage abrupt-drop monitoring circuit is effectively improved. However, the quantization logic is complex, and usually requires multiple cycles to obtain the voltage quantization result, and the real-time performance is poor. In general, the voltage drop phenomenon, especially the first-order voltage drop phenomenon (amplitude reduction >100mV, time <10 ns) with the greatest threat to the system, is still difficult to accurately and rapidly monitor by the existing digital voltage drop monitoring circuit. The design challenges include 1) the resolution of the voltage dip monitoring circuit is limited by the performance of the ring oscillator, but a ring oscillator design method oriented to high voltage sensitivity and load balancing is lacked, 2) the design thought based on a ring oscillator-counter can effectively widen the voltage detection range, but the traditional counter design can break the load balancing of an oscillator access node to cause jitter of a final quantized result, and 3) the quantized logic of the traditional digital voltage dip monitoring circuit is complex, a critical path is long, the maximum sampling rate is limited, or a plurality of periods are needed to obtain the final quantized result, namely hysteresis is serious. Disclosure of Invention The invention aims to provide a high-speed high-precisi