CN-116455339-B - Operational amplifier

CN116455339BCN 116455339 BCN116455339 BCN 116455339BCN-116455339-B

Abstract

Embodiments of the present disclosure provide an operational amplifier including an input stage circuit, an output stage control circuit, first and second slew rate enhancement circuits, and first and second transistors. The input stage circuit generates a differential output voltage according to a voltage difference between the first input voltage and the second input voltage. The output stage control circuit generates first and second control voltages from the differential output voltage. The first slew rate enhancement circuit increases the turn-off speed of the first transistor when the voltage difference transitions downward. The second slew rate enhancement circuit increases the turn-off speed of the second transistor when the voltage difference jumps upward. The first slew rate enhancement circuit comprises a first negative feedback circuit for slowing the turn-off speed of the first transistor to suppress the output voltage overshoot of the operational amplifier. The second slew rate enhancement circuit includes a second negative feedback circuit for slowing a turn-off speed of the second transistor to suppress an output voltage overshoot of the operational amplifier.

Inventors

ZHOU JIAN
ZHANG HAIBING

Assignees

圣邦微电子（北京）股份有限公司

Dates

Publication Date: 20260508
Application Date: 20230221

Claims (10)

1. An operational amplifier includes an input stage circuit, an output stage control circuit, a first slew rate enhancement circuit, a second slew rate enhancement circuit, a first transistor, and a second transistor, Wherein the input stage circuit is configured to amplify a voltage difference between a first input voltage from a first input terminal and a second input voltage from a second input terminal to generate a differential output voltage; The output stage control circuit is configured to generate a first control voltage and a second control voltage according to the differential output voltage and output the first control voltage and the second control voltage from a first output end and a second output end respectively, wherein the first control voltage and the second control voltage are respectively in negative correlation with the differential output voltage; The control electrode of the first transistor is coupled with the first output end of the output stage control circuit and the output end of the first conversion rate enhancement circuit, the first electrode of the first transistor is coupled with a first voltage end, and the second electrode of the first transistor is coupled with the output end of the operational amplifier and the second electrode of the second transistor; A control electrode of the second transistor is coupled to the second output end of the output stage control circuit and the output end of the second slew rate enhancement circuit, and a first electrode of the second transistor is coupled to a second voltage end; the first slew rate enhancement circuit is configured to adjust a voltage of a control electrode of the first transistor to increase an off-speed of the first transistor when the voltage difference transitions downward; the second slew rate enhancement circuit is configured to adjust a voltage of a control electrode of the second transistor to increase a turn-off speed of the second transistor when the voltage difference jumps upward; The first slew rate enhancement circuit comprises a first negative feedback circuit, the first negative feedback circuit is used for slowing down the adjustment amplitude of the voltage of the control electrode of the first transistor to inhibit the output voltage overshoot of the operational amplifier, and the second slew rate enhancement circuit comprises a second negative feedback circuit, and the second negative feedback circuit is used for slowing down the adjustment amplitude of the voltage of the control electrode of the second transistor to inhibit the output voltage overshoot of the operational amplifier.
2. The operational amplifier of claim 1, wherein the first slew rate enhancement circuit further comprises a first input circuit, a first internal load circuit, a second internal load circuit, a pull-up circuit, a first current source, a second current source, a third transistor, and a fourth transistor, Generating a first shunt and a second shunt from the first input voltage, the second input voltage, and a first current from a first current source, outputting the first shunt via a first node, and outputting the second shunt via a second node, wherein a sum of the first shunt and the second shunt is equal to the first current, and a ratio of the first shunt and the second shunt is inversely proportional to a voltage difference between the first input voltage and the second input voltage; A control electrode of the third transistor is coupled to the second electrode of the third transistor, the control electrode of the fourth transistor, the first input circuit and the second current source via the first node, and a first electrode of the third transistor is coupled to the first internal load circuit and the first negative feedback circuit; a first pole of the fourth transistor is coupled to the second internal load circuit, and a second pole of the fourth transistor is coupled to the first negative feedback circuit and the pull-up circuit; The first negative feedback circuit is coupled with the first input circuit and the third current source through the second node; The first internal load circuit is configured to control a voltage of the first pole of the third transistor according to a current flowing through the first internal load circuit; the second internal load circuit is configured to control a voltage of the first pole of the fourth transistor according to a current flowing through the second internal load circuit; The pull-up circuit is configured to control an amplitude by which a voltage of a control electrode of the first transistor is pulled up in accordance with a voltage of the second electrode of the fourth transistor; the first negative feedback circuit is configured to shunt a third current from the third current source to the first internal load circuit.
3. The operational amplifier of claim 2, wherein the first input circuit comprises a fifth transistor and a sixth transistor, The control electrode of the fifth transistor is coupled to the first input end, the first electrode of the fifth transistor is coupled to the first current source and the first electrode of the sixth transistor, and the second electrode of the fifth transistor is coupled to the first node; The control electrode of the sixth transistor is coupled to the second input terminal, and the second electrode of the sixth transistor is coupled to the second node.
4. The operational amplifier of claim 2, wherein the pull-up circuit comprises a seventh transistor, The control electrode of the seventh transistor is coupled to the second electrode of the fourth transistor, the first electrode of the seventh transistor is coupled to the first voltage terminal, and the second electrode of the seventh transistor is coupled to the control electrode of the first transistor.
5. The operational amplifier according to any one of claims 2 to 4, wherein the first negative feedback circuit includes an eighth transistor, and a ninth transistor, Wherein a control electrode of the eighth transistor is coupled to the second electrode of the fourth transistor and the second electrode of the ninth transistor, a first electrode of the eighth transistor is coupled to the first electrode of the third transistor, and a second electrode of the eighth transistor is coupled to the second node; The control electrode of the ninth transistor is coupled to the first bias voltage terminal, and the first electrode of the ninth transistor is coupled to the second node.
6. The operational amplifier of claim 1, wherein the second slew rate enhancement circuit further comprises a second input circuit, a third internal load circuit, a fourth internal load circuit, a pull-down circuit, a fourth current source, a fifth current source, a sixth current source, a tenth transistor, and an eleventh transistor, Generating a third shunt and a fourth shunt from the first input voltage, the second input voltage, and a fourth current from a fourth current source, the third shunt being output via a third node and the fourth shunt being output via a fourth node, wherein a sum of the third shunt and the fourth shunt is equal to the fourth current, a ratio of the third shunt and the fourth shunt being inversely proportional to a voltage difference between the first input voltage and the second input voltage; A control electrode of the tenth transistor is coupled to the second electrode of the tenth transistor, the control electrode of the eleventh transistor, and the fifth current source, and a first electrode of the tenth transistor is coupled to the second input circuit, the third internal load circuit, and the second negative feedback circuit via the third node; A first pole of the eleventh transistor is coupled to the fourth internal load circuit via the fourth node, and a second pole of the eleventh transistor is coupled to the second negative feedback circuit and the pull-down circuit; the second negative feedback circuit is coupled with the sixth current source; the third internal load circuit is configured to control a voltage of the first pole of the tenth transistor according to a current flowing through the third internal load circuit; the fourth internal load circuit is configured to control a voltage of the first pole of the eleventh transistor according to a current flowing through the fourth internal load circuit; The pull-down circuit is configured to control an amplitude by which a voltage of a control electrode of the second transistor is pulled down in accordance with a voltage of the second electrode of the eleventh transistor; The second negative feedback circuit is configured to shunt a sixth current from the sixth current source to the third internal load circuit.
7. The operational amplifier of claim 6, wherein the second input circuit comprises a twelfth transistor and a thirteenth transistor, Wherein a control electrode of the twelfth transistor is coupled to the first input terminal, a first electrode of the twelfth transistor is coupled to the fourth current source and the first electrode of the thirteenth transistor, and a second electrode of the twelfth transistor is coupled to the third node; the control electrode of the thirteenth transistor is coupled to the second input terminal, and the second electrode of the thirteenth transistor is coupled to the fourth node.
8. The operational amplifier of claim 6, wherein the pull-down circuit comprises a fourteenth transistor, The control electrode of the fourteenth transistor is coupled to the second electrode of the eleventh transistor, the first electrode of the fourteenth transistor is coupled to the second voltage terminal, and the second electrode of the fourteenth transistor is coupled to the control electrode of the second transistor.
9. The operational amplifier according to any one of claims 6 to 8, wherein the second negative feedback circuit includes a fifteenth transistor, and a sixteenth transistor, Wherein a control electrode of the fifteenth transistor is coupled to the second electrode of the eleventh transistor and the second electrode of the sixteenth transistor, a first electrode of the fifteenth transistor is coupled to the third node, and a second electrode of the fifteenth transistor is coupled to the first electrode of the sixteenth transistor and the sixth current source; The control electrode of the sixteenth transistor is coupled to the second bias voltage terminal.
10. An operational amplifier includes an input stage circuit, an output stage control circuit, first to sixteenth transistors, first to fourth resistors, first to sixth current sources, Wherein the input stage circuit is configured to amplify a voltage difference between a first input voltage from a first input terminal and a second input voltage from a second input terminal to generate a differential output voltage; The output stage control circuit is configured to generate a first control voltage and a second control voltage according to the differential output voltage and output the first control voltage and the second control voltage from a first output end and a second output end respectively, wherein the first control voltage and the second control voltage are respectively in negative correlation with the differential output voltage; The control electrode of the first transistor is coupled with the first output end of the output stage control circuit and the second electrode of the seventh transistor, the first electrode of the first transistor is coupled with the first voltage end, and the second electrode of the first transistor is coupled with the output end of the operational amplifier and the second electrode of the second transistor; The control electrode of the second transistor is coupled with the second output end of the output stage control circuit and the second electrode of the fourteenth transistor, and the first electrode of the second transistor is coupled with a second voltage end; a control electrode of the third transistor is coupled with a second electrode of the third transistor, a control electrode of the fourth transistor, a second electrode of the fifth transistor and a second current source, and a first electrode of the third transistor is coupled with a first end of the first resistor and a first electrode of the eighth transistor; A first pole of the fourth transistor is coupled to a first end of a second resistor, and a second pole of the fourth transistor is coupled to the control pole of the seventh transistor, the control pole of the eighth transistor, and the second pole of the ninth transistor; a second end of the first resistor is coupled to a second end of the second resistor and the first voltage end; A control electrode of the fifth transistor is coupled to the first input terminal, and a first electrode of the fifth transistor is coupled to the first current source and a first electrode of the sixth transistor; a control electrode of the sixth transistor is coupled to the second input terminal, and a second electrode of the sixth transistor is coupled to the second electrode of the eighth transistor, the first electrode of the ninth transistor, and a third current source; A first pole of the seventh transistor is coupled to the first voltage terminal; the control electrode of the ninth transistor is coupled with the first bias voltage end; A control electrode of a tenth transistor is coupled to the second electrode of the tenth transistor, the control electrode of the eleventh transistor and the fifth current source, and a first electrode of the tenth transistor is coupled to the second electrode of the twelfth transistor, the first electrode of the fifteenth transistor and the first end of the third resistor; a first pole of the eleventh transistor is coupled to a second pole of the thirteenth transistor and a first end of a fourth resistor, and a second pole of the eleventh transistor is coupled to a control pole of the fourteenth transistor, a control pole of the fifteenth transistor, and a second pole of the sixteenth transistor; a second end of the third resistor is coupled to the second end of the fourth resistor and the second voltage end; A control electrode of the twelfth transistor is coupled to the first input terminal, and a first electrode of the twelfth transistor is coupled to the fourth current source and the first electrode of the thirteenth transistor; A control electrode of the thirteenth transistor is coupled to the second input terminal; A first pole of the fourteenth transistor is coupled to the second voltage terminal; a second pole of the fifteenth transistor is coupled to the first pole of the sixteenth transistor and the sixth current source; The control electrode of the sixteenth transistor is coupled to the second bias voltage terminal.

Description

Operational amplifier Technical Field Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to an operational amplifier. Background An operational amplifier is a common integrated circuit, and is widely used in various circuits to realize different functions, such as signal amplification, stable output, signal driving, etc. Slew Rate (Slew Rate) is a parameter that characterizes the operational amplifier's ability to handle large signals. Some applications require an operational amplifier with a relatively high slew rate. Disclosure of Invention Embodiments described herein provide an operational amplifier. According to a first aspect of the present disclosure, an operational amplifier is provided. The operational amplifier includes an input stage circuit, an output stage control circuit, a first slew rate enhancement circuit, a second slew rate enhancement circuit, a first transistor, and a second transistor. Wherein the input stage circuit is configured to amplify a voltage difference between a first input voltage from the first input terminal and a second input voltage from the second input terminal to generate a differential output voltage. The output stage control circuit is configured to generate a first control voltage and a second control voltage from the differential output voltage and output the first control voltage and the second control voltage from the first output terminal and the second output terminal, respectively. Wherein the first control voltage and the second control voltage are inversely related to the differential output voltage, respectively. The control electrode of the first transistor is coupled to the first output end of the output stage control circuit and the output end of the first conversion rate enhancement circuit. The first electrode of the first transistor is coupled to the first voltage terminal. The second pole of the first transistor is coupled to the output of the operational amplifier and the second pole of the second transistor. The control electrode of the second transistor is coupled to the second output end of the output stage control circuit and the output end of the second slew rate enhancement circuit. The first electrode of the second transistor is coupled to the second voltage terminal. The first slew rate enhancement circuit is configured to adjust a voltage of a control electrode of the first transistor to increase an off-speed of the first transistor when the voltage difference transitions downward. The second slew rate enhancement circuit is configured to adjust the voltage at the control electrode of the second transistor to increase the turn-off speed of the second transistor when the voltage difference transitions upward. Wherein the first slew rate enhancement circuit comprises a first negative feedback circuit. The first negative feedback circuit is used for slowing down the adjustment amplitude of the voltage of the control electrode of the first transistor so as to restrain the output voltage overshoot of the operational amplifier. The second slew rate enhancement circuit comprises a second negative feedback circuit. The second negative feedback circuit is used for slowing down the adjustment amplitude of the voltage of the control electrode of the second transistor so as to restrain the output voltage overshoot of the operational amplifier. In some embodiments of the present disclosure, the first conversion rate enhancement circuit further includes a first input circuit, a first internal load circuit, a second internal load circuit, a pull-up circuit, a first current source, a second current source, a third transistor, and a fourth transistor. The first input circuit is configured to generate a first shunt and a second shunt according to a first input voltage, a second input voltage, and a first current from a first current source, output the first shunt via a first node, and output the second shunt via a second node. Wherein the sum of the first and second current branches is equal to the first current. The ratio of the first and second branches is inversely proportional to the voltage difference between the first and second input voltages. The control electrode of the third transistor is coupled to the second electrode of the third transistor, the control electrode of the fourth transistor, the first input circuit and the second current source via the first node. The first pole of the third transistor is coupled to the first internal load circuit and the first negative feedback circuit. The first pole of the fourth transistor is coupled to the second internal load circuit. The second pole of the fourth transistor is coupled to the first negative feedback circuit and the pull-up circuit. The first negative feedback circuit is coupled to the first input circuit and the third current source via the second node. The first internal load circuit is configured to control a voltage of a first po