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CN-116472716-B - Charge-demultiplexed high-speed CMOS time delay integral imaging

CN116472716BCN 116472716 BCN116472716 BCN 116472716BCN-116472716-B

Abstract

Apparatus, methods, and techniques are provided for performing readout of a plurality (N) of Time Delay Integration (TDI) pixel registers to receive respective signal charges at a plurality (N) of Sense Nodes (SN). The readout uses a plurality of N Charge Steering (CST) gates to steer and demultiplex the respective charges from the respective pixel registers to the corresponding SNs. An output is provided from SN to produce a corresponding digital value (e.g., by parallel conversion using an ADC). In one embodiment, the charge is transferred vertically to the CST to be demultiplexed horizontally to SN. CST may be configured in a multi-stage configuration to aid in good charge transfer. CST may be associated with barrier implant to assist in proper charge steering.

Inventors

  • H.J.Li
  • P. Donegan
  • N.Ou
  • S.K.Hong

Assignees

  • 特励达数字成像有限公司

Dates

Publication Date
20260508
Application Date
20201030
Priority Date
20200910

Claims (20)

  1. 1. A complementary metal oxide semiconductor time delay integral high fidelity imaging method, comprising: performing a readout of a plurality (N) of time delay integration TDI pixel registers to receive respective signal charges at a plurality (N) of sense nodes, wherein the readout uses a plurality (N) of charge steering gates to steer and demultiplex respective charges from the respective pixel registers to the plurality of sense nodes, and Outputs from the plurality of sense nodes are provided to produce respective digital values.
  2. 2. The method of claim 1, comprising resetting the plurality of sense nodes in parallel to receive the respective signal charges.
  3. 3. The method of claim 2, wherein resetting the plurality of sense nodes in parallel comprises clearing the plurality of sense nodes to a reset drain voltage by resetting gates in parallel.
  4. 4. A method according to any one of claims 1 to 3, wherein the charge is transferred vertically, guided by the plurality (N) of charge-guiding gates, to be demultiplexed horizontally to the plurality of sensing nodes.
  5. 5. The method of any of claims 1-4, wherein the plurality (N) of charge directors define a last stage of a charge director gate, and wherein the method comprises transferring the charge to a previous stage of the director gate in a cascaded manner to be directed to the last stage of the charge director gate.
  6. 6. The method of any of claims 1-5, wherein each of the plurality (N) of charge-steering gates receives a respective barrier implant BIM, the barrier implants defining a barrier when each charge-steering gate clock is low.
  7. 7. The method according to any one of claims 1 to 6, comprising: Clocking respective ones of the pixel registers, respective ones of the charge-steering gates, and respective ones of a plurality (N) of isolated ISO registers using a multiphase image register clock to transfer charge; using respective gate electrodes Clx associated with respective phases of the multiphase image register clock, respective Clx of which are horizontally consecutive to eliminate x-y matrix addressing of the respective Clx in the ISO register, and A channel stop layer is used between channels extending from respective ones of the plurality (N) of charge-directing gates to respective ones of the plurality (N) of sense nodes to avoid charge mixing between channels in the ISO register.
  8. 8. The method of any of claims 4-6, wherein, to transfer charge from one of the pixel registers to a corresponding one of the charge-steering gates, only the corresponding one of the charge-steering gates is high and the remaining charge-steering gate clocks of the plurality (N) of charge-steering gates are low.
  9. 9. The method of any one of claims 1 to 8, wherein each of the sense nodes is coupled to a respective source follower SF to provide a respective signal voltage for conversion to the respective digital value.
  10. 10. The method of any of claims 1 to 9, wherein the output is provided to perform parallel conversion of the plurality of sense nodes to produce the respective digital values.
  11. 11. The method of claim 10, wherein performing the parallel conversion comprises: Parallel conversion of the corresponding signal charges into corresponding signal voltages, and The respective signal voltages are converted in parallel into respective digital values.
  12. 12. The method of claim 11, wherein converting the respective signal voltages comprises ping-pong sample and hold S/H capacitor array circuitry: Sampling the respective reference voltages for the current time in parallel to the respective first reference capacitors of the respective S/H capacitor array; Sampling the respective earlier time signal voltages in parallel to the respective signal capacitors, and The respective correlated double sampled CDS voltages from the respective earlier time reference voltages sampled at the respective second reference capacitors and the respective earlier time signal voltages sampled at the signal capacitors are provided in parallel to respective column-to-parallel analog-to-digital converters ADCs to generate respective earlier time digital values.
  13. 13. The method of claim 12, further comprising: receiving the respective reference voltage to the respective second reference capacitor and the current signal voltage to the respective signal capacitor at a next time further in parallel, and Respective CDS voltages from respective current reference voltages sampled at the respective first reference capacitors and respective current signal voltages sampled at the signal capacitors are provided in parallel to the respective column-parallel ADCs to produce respective current digital values.
  14. 14. The method of any of claims 11 to 13, wherein converting the respective signal voltages to respective digital values in parallel is performed at a current time and further in parallel with reading out a plurality of respective signal charges at a next time to the plurality of sense nodes.
  15. 15. The method of any of claims 1-14, wherein the reading out of a plurality of TDI registers to receive the respective signal charges is performed at a current time and further in parallel with converting a respective earlier time signal voltage to a respective earlier time digital value.
  16. 16. The method of any of claims 1-15, wherein the method is performed by a high-speed CMOS TDI image sensor comprising a plurality of charge-coupled device CCD pixels arranged in a CCD pixel matrix, a column slice of the CCD pixels comprising the plurality (N) of TDI pixel registers, a plurality (N) of isolated ISO registers comprising the plurality (N) of CSTs, a plurality of output structures comprising the plurality (N) of sensing nodes, a global reset structure, and a plurality of SFs, and a plurality (N) of parallel conversion components, each parallel conversion component comprising an S/H capacitor array and a column-parallel ADC.
  17. 17. The method according to claim 16, wherein: the forward sense node is connected to one end of the CCD pixel matrix; the reverse sense node is connected with the other end of the CCD pixel matrix and The method is performed using one of i) the forward sense node and ii) the reverse sense node as the plurality of (N) sense nodes in response to a scan direction.
  18. 18. A cmos time delay integral high-fidelity imaging device comprising: A plurality of (N) time delay integration TDI pixel registers; A plurality of (N) isolated ISO registers including a plurality of (N) charge-steering gates coupled to the plurality of (N) TDI pixel registers; A plurality of N output structures including a plurality of N sense nodes coupled to receive respective signal charges read out from the plurality of N TDI pixel registers, the respective signal charges being directed and demultiplexed by the plurality of N charge directing gates, the plurality of N sense nodes coupled to provide outputs to generate digital values, Wherein: Each of the plurality of N sense nodes is configured with circuitry providing a parallel reset function, an Each of the plurality of (N) sense nodes is coupled to a plurality of (N) sample and hold S/H capacitor circuits and a plurality of (N) column-parallel analog-to-digital converters ADCs via a plurality of (N) source followers SF to generate in parallel a respective digital value for each of the respective signal charges.
  19. 19. The apparatus of claim 18, wherein charge is transferred vertically, directed by the plurality (N) of charge directing gates, to be demultiplexed horizontally to the plurality of sense nodes.
  20. 20. The apparatus of claim 18 or 19, wherein the plurality (N) of charge-steering gates define a last stage of charge-steering gates, and wherein the apparatus comprises a previous stage of steering gates coupled to the TDI pixel register and the last stage of charge-steering gates in a cascaded manner to steer the charge to the last stage of charge-steering gates.

Description

Charge-demultiplexed high-speed CMOS time delay integral imaging Technical Field The present disclosure relates to Complementary Metal Oxide Semiconductor (CMOS) Time Delay Integration (TDI) high-fidelity imaging methods and apparatus therefor for parallel readout operations, and more particularly to charge demultiplexing high-speed charge-coupled CMOS Time Delay Integration (TDI) imaging. Background In a conventional CMOS TDI imager, the following row-by-row readout operation is performed. This sequential operation limits the speed of the sensor. 1. The Sense Node (SN) is reset to a reset drain Voltage (VDD) through a reset gate (RST). 2. The signal charge of the final TDI stage is transferred to SN.3. The signal charge is converted into a signal voltage at SN and output via a Source Follower (SF). 4. The analog signal voltage is then converted to a digital value by an analog-to-digital converter (ADC). In the current state-of-the-art CMOS TDI imagers, at least about 3 mus is required to complete one TDI line process (i.e., a maximum line rate of about 300 kHz). Disclosure of Invention Embodiments herein relate to a high-speed charge-coupled CMOS TDI image sensor in which a plurality of charge-coupled device (CCD) pixels are arranged in a matrix. In one embodiment, a column slice of such a pixel array includes M TDI imaging pixels, N charge-steering gates (CST), N SNs, a global reset structure (e.g., RST and VDD), and N parallel readout structures, where the N parallel readout structures include N SFs, N sample-and-hold (S/H) capacitor circuits for Correlated Double Sampling (CDS) operations, and N column-parallel ADCs, where N is equal to or less than M. Apparatus, methods, and techniques are provided for performing readout of a plurality (N) of TDI pixel registers to receive respective signal charges at a plurality (N) of SNs. The readout uses multiple (N) CSTs to direct and demultiplex the respective charges from the respective pixel registers to the corresponding SNs. An output is provided from SN to produce a corresponding digital value (e.g., by parallel conversion using an ADC). In one embodiment, the charge is transferred vertically to the CST to be demultiplexed horizontally to SN. CST may be configured in a multi-stage configuration to aid in good charge transfer. CST may be associated with barrier implant to assist in proper charge steering. The device may be a high-speed charge coupled CMOS TDI image sensor in which a plurality of CCD pixels are arranged in a matrix. Such an image sensor may be configured for bi-directional operation. In one embodiment, a method is provided that includes performing a readout of a plurality (N) of Time Delay Integration (TDI) pixel registers to receive respective signal charges at a plurality (N) of sensing nodes, wherein the readout uses a plurality (N) of charge-steering gates to steer and demultiplex the respective charges from the respective pixel registers to the plurality of sensing nodes, and providing outputs from the plurality of sensing nodes to produce respective digital values. In one embodiment, the method is performed by a high-speed CMOS TDI image sensor comprising a plurality of Charge Coupled Device (CCD) pixels arranged in a CCD pixel matrix, a column slice of the CCD pixels comprising a plurality of N TDI pixel registers, a plurality of N Isolation (ISO) registers comprising a plurality of N CSTs, a plurality of output structures comprising a plurality of N sense nodes, a global reset structure, and a plurality of SF, and a plurality of N parallel conversion components, each parallel conversion component comprising an S/H capacitor array and a column-parallel ADC. In one embodiment, an apparatus is provided that includes circuitry configured to perform a method according to any of the method embodiments herein. In one embodiment, an apparatus is provided that includes a plurality (N) of Time Delay Integration (TDI) pixel registers, a plurality (N) of Isolation (ISO) registers including a plurality (N) of charge-steering gates coupled to the plurality (N) of TDI pixel registers, a plurality (N) of output structures including a plurality (N) of sense nodes coupled to receive respective signal charges read from the plurality (N) of TDI pixel registers, the respective signal charges being steered and demultiplexed by the plurality (N) of charge-steering gates, the plurality (N) of sense nodes coupled to provide outputs to produce digital values. In one embodiment, each of the plurality (N) of sense nodes is configured with circuitry that provides a parallel reset function. In one embodiment, each of the plurality of (N) sense nodes is coupled to a plurality of (N) sample and hold (S/H) capacitor circuits and a plurality of (N) column-parallel analog-to-digital converters (ADCs) via a plurality of (N) Source Followers (SFs) to generate a respective digital value for each respective signal charge in parallel. In one embodiment, the apparatus compris