CN-116481684-B - High-temperature pressure sensing chip based on monocrystalline silicon wafer and three-dimensional integration method

CN116481684BCN 116481684 BCN116481684 BCN 116481684BCN-116481684-B

Abstract

The invention discloses a high-temperature pressure sensing chip based on a monocrystalline silicon wafer and a three-dimensional integration method, the manufacturing process of the chip comprises a force sensitive resistor manufacturing step, an insulating isolation step, a high-temperature resistant electrode and interconnection line manufacturing step, a pressure sensitive membrane etching step and a bonding step. The invention uses the method of etching the insulating isolation groove around the force sensitive resistor, filling and covering the insulating layer, and precisely corroding the lower layer body silicon of the force sensitive resistor, avoids the problem of failure of the traditional monocrystalline silicon pn junction isolation high-temperature leakage current, does not depend on the expensive materials such as SOI wafer, silicon carbide wafer and the like, realizes the mutual insulation isolation between the Wheatstone bridge force sensitive resistors by using the common monocrystalline silicon wafer, and meets the high-temperature working requirement. The airtight leadless bonding method based on the through silicon vias further improves the reliability of the pressure sensing chip. Meanwhile, the manufacturing method is completely compatible with a silicon-based CMOS process, and system-on-chip integration can be achieved.

Inventors

LIU GUANDONG
LIU NAN
WANG WEIHAO
LI JIE
WANG CHUANZHI
CAO RONG

Assignees

之江实验室

Dates

Publication Date: 20260508
Application Date: 20230612

Claims (10)

1. The high-temperature pressure sensing chip based on the monocrystalline silicon wafer is characterized in that the manufacturing process comprises the following steps: A step of manufacturing a force-sensitive resistor, in which a force-sensitive resistor sensitive to pressure is manufactured on a monocrystalline silicon wafer; Etching an insulating isolation groove around the force sensitive resistor, depositing an insulating layer in the insulating isolation groove, on the upper surface of the force sensitive resistor and the upper surface of the monocrystalline silicon wafer, and depositing a passivation layer on the lower surface of the monocrystalline silicon wafer, wherein the insulating isolation groove is only arranged on the side surface of the force sensitive resistor, and no insulating isolation groove is arranged below the force sensitive resistor; Etching an insulating layer in an ohmic contact area of the force sensitive resistor to manufacture high-temperature-resistant lead interconnection; etching the passivation layer until the silicon on the lower surface of the force-sensitive resistor is completely etched and removed to obtain a pressure-sensitive membrane; And a bonding step, wherein the pressure sensitive membrane and the substrate are subjected to vacuum bonding to form the high-temperature pressure sensing chip with the vacuum reference cavity.
2. The chip of claim 1, wherein the force sensitive resistor manufacturing step is: And photoetching the shape of the force-sensitive resistor of the Wheatstone bridge on the upper surface of the monocrystalline silicon wafer, carrying out p-type ion implantation, removing photoresist, and carrying out high-temperature annealing to form the p-type force-sensitive resistor with uniform impurity concentration distribution along the depth direction.
3. The chip of claim 2, wherein the doping concentration of the force sensitive resistor after annealing is greater than 3e18 cm -3 .
4. The chip of claim 1, wherein the insulating isolating step comprises: Etching an insulating isolation groove, namely photoetching and etching an insulating isolation groove surrounding the force sensitive resistor on the upper surface of the monocrystalline silicon wafer, wherein the depth of the insulating isolation groove is larger than or equal to that of the force sensitive resistor; and the insulating layer deposition sub-step is to deposit passivation thick films on the upper surface of the force sensitive resistor and the upper surface of the monocrystalline silicon wafer in the insulating isolation groove and respectively deposit passivation layers on the lower surface of the monocrystalline silicon wafer.
5. The chip of claim 4, wherein the passivation thick film is grown by dry oxidation to form a dense silicon dioxide layer on the surfaces of the monocrystalline silicon wafer and the insulating isolation trench, by low pressure chemical vapor deposition to form a dense silicon dioxide layer or a silicon nitride layer thicker than the silicon dioxide layer on the surfaces of the monocrystalline silicon wafer and the insulating isolation trench for insulating filling and covering; The passivation layer is obtained by dry oxygen oxidation and low-pressure chemical vapor deposition of a silicon dioxide layer or a silicon nitride layer on the upper surface of the monocrystalline silicon wafer and simultaneously deposition on the lower surface.
6. The chip of claim 5, wherein in the process of growing the passivation thick film, the thick film is continuously deposited on the upper surface of the wafer by one or more of plasma enhanced chemical vapor deposition silicon dioxide, low pressure chemical vapor deposition polysilicon, sputtering or evaporating or electroplating a metal layer, according to the performance requirements of the pressure sensing chip, before lapping and polishing.
7. The chip of claim 1, wherein the high temperature resistant wire interconnect manufacturing step comprises: Photoetching and etching an insulating layer above an ohmic contact region of the force sensitive resistor to form an ohmic contact window; and a step of lead interconnection growth, which is to carry out heavy doping ion implantation and annealing on the silicon in the ohmic contact window, grow refractory metal silicide on the silicon of the ohmic contact window and grow high-temperature-resistant lead interconnection.
8. The chip of claim 7, wherein the lead interconnection structure is a titanium/titanium nitride/titanium/copper high temperature resistant composite electrode structure compatible with copper-tin through-silicon via process or a titanium/titanium nitride/platinum/gold high temperature resistant composite electrode structure compatible with gold-tin transient liquid phase bonding process.
9. The chip of claim 1, wherein the pressure sensitive diaphragm etching step comprises the sub-steps of: etching window, namely photoetching and etching passivation layer on the lower surface of the monocrystalline silicon wafer to form a window; A protective layer application sub-step of applying a protective layer on the upper surface of the monocrystalline silicon wafer; Wet chemical etching to anisotropically etch the lower surface of the monocrystalline silicon wafer through the window by wet chemical etching until the monocrystalline silicon layer on the lower surface of the force-sensitive resistor is not directly connected through any bulk silicon layer; and a protective layer removing sub-step, namely removing the passivation layer on the lower surface and the protective layer on the upper surface to obtain the C-type pressure sensitive membrane.
10. A three-dimensional integration method of the high-temperature pressure sensing chip based on the single crystal silicon wafer as set forth in any one of claims 1 to 9, comprising: For the bottom bonding mode, vacuum bonding is carried out on one side of the opening of the pressure sensitive membrane and the substrate, and then the pressure sensitive membrane is inversely bonded to the silicon adapter plate to form a three-dimensional integrated structure with other electronic chips; For the top bonding mode, the non-opening side of the pressure sensitive membrane is vacuum bonded with the substrate, and meanwhile, the electrical signal is led out based on TSV, and then the pressure sensitive membrane is flip-chip bonded onto the silicon adapter plate to form a three-dimensional integrated structure with other electronic chips.

Description

High-temperature pressure sensing chip based on monocrystalline silicon wafer and three-dimensional integration method Technical Field The invention belongs to the technical field of electronics, and particularly relates to a high-temperature pressure sensing chip based on a monocrystalline silicon wafer and a three-dimensional integration method. Background In recent years, information technologies such as the internet of things, big data, artificial intelligence and the like are rapidly developed, and higher requirements are put on functions of an electronic system. The electronic system not only needs to have strong data computing capacity and storage capacity, but also needs to have sensitive sensing capacity to the external environment, so that chips with different functions are integrated together to form a system, and a 'sense memory calculation integrated' system with more complex functions is formed. The sensing chip is equivalent to the perception of the external environment by the five sense organs of a person, integrates the multi-physical-quantity sensing chip into a system, and has important significance for realizing the real-time monitoring and control of complex physical quantity in modern industrial scenes. The high-temperature pressure sensing chip is an important physical quantity sensor in the modern industry and is widely applied to pressure measurement in high-temperature environments such as aerospace, deep well exploration, reaction vessel control and the like. Although the piezoresistive pressure sensing chip based on monocrystalline silicon has the advantages of mature process, high sensitivity and good linearity, is widely applied in low-temperature environments below 120 ℃, when the piezoresistive pressure sensing chip works in high-temperature environments above 120 ℃, the performance of insulating isolation by means of pn firm stress-sensitive resistors and substrate silicon can fail due to aggravation of leakage current, so that the piezoresistive device cannot work normally. Therefore, it is considered that a pressure sensing chip operating in a high temperature environment of 120 ℃ or more cannot be manufactured based on a single crystal silicon wafer. In order to meet the requirement of pressure measurement in a high-temperature environment of above 120 ℃, a high-temperature pressure sensing chip based on Silicon On Insulator (SOI) is developed, an insulating buried oxide layer is introduced between top silicon and substrate silicon on the basis of a monocrystalline silicon wafer, leakage current between a silicon resistor and a silicon substrate is effectively isolated, and the problem of high-temperature isolation failure of a conventional monocrystalline silicon pn junction is solved. However, SOI wafers are expensive, often more than ten times as expensive as single crystal silicon wafers, limiting the large-scale application of high temperature pressure sensing chips. Disclosure of Invention In order to solve the problem of high-temperature failure of pn junction isolation of a common monocrystalline silicon wafer, the embodiment of the application aims to provide a high-temperature pressure sensing chip and a three-dimensional integration method based on the monocrystalline silicon wafer, which not only use the common monocrystalline silicon wafer to manufacture the pressure sensing chip capable of working in a high-temperature environment of more than 120 ℃, but also are fully compatible with a silicon-based CMOS (complementary metal oxide semiconductor) process, and can realize System-on-wafer (SOW) integration. According to a first aspect of an embodiment of the present application, there is provided a high temperature pressure sensing chip based on a monocrystalline silicon wafer, the manufacturing process of which includes: A step of manufacturing a force-sensitive resistor, in which a force-sensitive resistor sensitive to pressure is manufactured on a monocrystalline silicon wafer; Etching an insulating isolation groove around the force sensitive resistor, depositing an insulating layer in the insulating isolation groove, on the upper surface of the force sensitive resistor and the upper surface of the monocrystalline silicon wafer, and depositing a passivation layer on the lower surface of the monocrystalline silicon wafer; Etching an insulating layer in an ohmic contact area of the force sensitive resistor to manufacture high-temperature-resistant lead interconnection; etching the passivation layer until the silicon on the lower surface of the force-sensitive resistor is completely etched and removed to obtain a pressure-sensitive membrane; And a bonding step, wherein the pressure sensitive membrane and the substrate are subjected to vacuum bonding to form the high-temperature pressure sensing chip with the vacuum reference cavity. Further, the force sensitive resistor manufacturing steps are as follows: And photoetching the shape of the force-sensitive resis