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CN-116482518-B - MIV test circuit and test method based on voltage divider

CN116482518BCN 116482518 BCN116482518 BCN 116482518BCN-116482518-B

Abstract

The invention belongs to the field of test circuits, and particularly relates to an MIV test circuit and a test method based on a voltage divider. The common test unit is used for switching different test modes to detect whether open circuit faults, short circuit faults or electric leakage faults exist in the MIV, the voltage dividing unit is used for establishing a test model of the MIV group, and the voltage comparison unit is used for judging whether the voltage of the test point is in a normal voltage range. The invention provides an MIV test circuit and a test method based on a voltage divider, which are used for solving the problem that the detectable fault range in the prior art is limited.

Inventors

  • YANG ZHIMING
  • XIAO ZIWEN
  • TIAN LI
  • YU YANG
  • LI KANGRONG
  • QIAO LIYAN

Assignees

  • 哈尔滨工业大学

Dates

Publication Date
20260508
Application Date
20230516

Claims (10)

  1. 1. The MIV test circuit based on the voltage divider is characterized by comprising a common test unit, a voltage dividing unit and a voltage comparison unit The public test unit is used for switching different test modes so as to detect whether an open circuit fault, a short circuit fault or a leakage fault exists in the MIV; The voltage dividing unit is used for establishing a test model of the MIV group; the voltage comparison unit is used for judging whether the voltage of the test point is in a normal voltage range or not; The public test unit is connected with the voltage comparison unit through the voltage division unit; The public test unit is connected with the voltage dividing unit, and the voltage dividing unit is connected with the voltage comparison unit; The public test unit (1) comprises a test controller, a first test special MIV, a second test special MIV and a third test special MIV, wherein the first test special MIV, the second test special MIV and the third test special MIV are all arranged on a middle-layer chip, and the test controller is arranged on an upper-layer chip; The voltage division unit (2) comprises an upper chip voltage division unit and a lower chip voltage division unit; the voltage comparison unit (3) comprises a first voltage comparator (31) and a second voltage comparator (32); The first voltage comparator and the second voltage comparator form a double-limit voltage comparator.
  2. 2. The MIV test circuit according to claim 1, wherein one output terminal of the test controller is connected to an address input terminal of a multiplexer of the voltage dividing unit in the upper chip, and the address input terminal of the multiplexer of the voltage dividing unit in the lower chip is connected to the other output terminal of the test controller through the test dedicated MIV; After the first test special MIV, the second test special MIV and the third test special MIV are connected in parallel, one end connected with the upper chip is the MIV head end, and one end connected with the lower chip is the MIV tail end; The first ends of the first special MIV, the second special MIV and the third special MIV are connected with two output ends of the test controller, and the tail ends of the first special MIV, the second special MIV and the third special MIV are connected with address input ends of multiplexers in the lower chip.
  3. 3. The MIV test circuit according to claim 2, wherein the voltage dividing unit (2) comprises a one-out-of-two multiplexer (22), an i-th-of-four multiplexer, an i-th input resistor R I1_i , an i-th input resistor R I2_i , a voltage dividing resistor R D1 , and a voltage dividing resistor R D2 ; The input end 0 of the alternative multiplexer (22) is connected with one end of the divider resistor R D1 , the input end 1 of the alternative multiplexer is connected with one end of the divider resistor R D2 , and the output end of the alternative multiplexer is connected with the ground.
  4. 4. The MIV test circuit according to claim 2, wherein the voltage divider unit (2) comprises a one-out-of-four multiplexer, wherein the input terminal 0 of the one-out-of-four multiplexer is connected to a power supply, the input terminal 1 of the one-out-of-four multiplexer is connected to one end of the input resistor R I1_1 , the input terminal 2 of the one-out-of-four multiplexer is connected to one end of the input resistor R I2_1 , the input terminal 3 of the one-out-of-four multiplexer is connected to one end of the functional input FI, the address input terminals a 0 、A 1 of the one-out-of-four multiplexer are all connected to one end of the test controller, and the output terminal of the one-out-of-four multiplexer is connected to the head end of the first tested MIV; The input end 0 of the fourth selected multiplexer is connected with the tail end of the i-1 tested MIV, the input end 1 of the fourth selected multiplexer is connected with one end of an input resistor R I1_i , the input end 2 of the fourth selected multiplexer is connected with one end of an input resistor R I2_i , the input end 3 of the fourth selected multiplexer is connected with one end of a functional input FI, the address input end A 0 、A 1 of the fourth selected multiplexer is connected with the tail end of the special MIV, the output end of the fourth selected multiplexer is connected with the tail end of the i-1 tested MIV, the input end 0 of the fourth selected multiplexer is connected with the head end of the i-1 tested MIV, the input end 1 of the fourth selected multiplexer is connected with one end of an input resistor R I1_i , the input end 2 of the fourth selected multiplexer is connected with one end of an input resistor R I2_i , the input end 3 of the fourth selected multiplexer is connected with one end of the functional input FI, the output end of the fourth selected multiplexer is connected with the first end of the special MIV, and the first end of the fourth selected multiplexer is connected with the first end 35V.
  5. 5. The voltage divider-based MIV test circuit according to claim 4, wherein one end of the input resistor R I1_1 is connected with a power supply, the other end of the input resistor R I1_1 is connected with the input end 1 of the first fourth multiplexer, one end of the i-th input resistor R I1_i is connected with the tail end of the i-1-th tested MIV, the other end of the i-th input resistor R I1_i is connected with the input end 1 of the i-th fourth multiplexer, one end of the i-th input resistor R I1_i is connected with the head end of the i-1-th tested MIV, and the other end of the i-th input resistor R I1_i is connected with the input end 1 of the i-th fourth multiplexer; One end of an input resistor R I2_1 is connected with a power supply, the other end of the input resistor R I2_1 is connected with the input end 2 of the first fourth multiplexer, one end of an i input resistor R I2_i is connected with the tail end of the i-1 tested MIV, the other end of the i input resistor R I2_i is connected with the input end 2 of the i fourth multiplexer, one end of an i input resistor R I2_i is connected with the head end of the i-1 tested MIV, and the other end of the i input resistor R I2_i is connected with the input end 2 of the i fourth multiplexer; One end of a divider resistor R D1 and one end of a divider resistor R D1 are connected with the head end of the n-th tested MIV, and the other end of the divider resistor R D1 is connected with the input end 0 of the alternative multiplexer; One end of the divider resistor R D2 is connected with the head end of the n-th tested MIV, and the other end of the divider resistor R D2 is connected with the input end 1 of the alternative multiplexer.
  6. 6. The voltage divider-based MIV test circuit according to claim 1, wherein the positive input terminal of the first voltage comparator is connected to the head terminal of the nth tested MIV, the negative input terminal of the first voltage comparator is connected between the resistor R VC_1 and the resistor R VC_2 , and the output terminal of the first voltage comparator is connected to the output terminal of the second voltage comparator; The positive input end of the first voltage comparator is connected with the head end of the n-th tested MIV, the negative input end of the first voltage comparator is connected between the resistor R VC_1 and the resistor R VC_2 , and the output end of the first voltage comparator is connected with the output end of the second voltage comparator to form an output end V out of the whole test circuit; One end of the resistor R VC_1 is connected with a power supply, the other end of the resistor R VC_1 is connected with the negative input end of the first voltage comparator, One end of the resistor R VC_2 is connected with the negative input end of the first voltage comparator, and the other end of the resistor R VC_2 is connected with the ground; One end of the resistor R VC_3 is connected with a power supply, the other end of the resistor R VC_3 is connected with the negative input end of the second voltage comparator, One end of the resistor R VC_4 is connected with the negative input end of the second voltage comparator, and the other end of the resistor R VC_4 is connected with the ground; One end of the resistor R VC_5 is connected with a power supply, and the other end of the resistor R VC_5 is connected with an output end V out of the whole test circuit.
  7. 7. A method of testing a voltage divider based MIV test circuit using the above voltage divider based MIV test circuit of any one of claims 1-6, the method comprising the steps of: Step 1, executing open circuit fault detection of the whole MIV group, outputting a 10 instruction to an i fourth multiplexer and a1 instruction to a second multiplexer by a test controller, and outputting a test output signal V out_1 by a test circuit; step 2, simultaneously executing the leakage fault detection of the whole MIV group and the short circuit fault detection of the first half MIV group, outputting a '01' instruction to an i fourth alternative multiplexer, outputting a '00' instruction to the i fourth alternative multiplexer, outputting a '0' instruction to the second alternative multiplexer, and outputting a test output signal V out_2 by a test circuit; Step 3, executing short-circuit fault detection on the second half group of MIVs, outputting a '00' instruction to an i fourth selected multiplexer, outputting a '01' instruction to the i fourth selected multiplexer, outputting a '0' instruction to a second selected multiplexer, and outputting a test output signal V out_3 by a test circuit; Step 4, judging whether the MIV group has faults or not based on the output signals V out_1 , V out_2 and V out_3 obtained in the steps 1-3, if the test output signals V out_1 、V out_2 and V out_3 are both high levels, the tested MIV group has no faults, and if any 1 of the test output signals V out_1 、V out_2 and V out_3 have low levels, the tested MIV group has faults.
  8. 8. The method of claim 7, wherein the electrical models of the MIV group in the fault-free state are each equivalent to an RC circuit model consisting of a resistor R MIV and a capacitor C MIV , wherein the resistor R MIV is the on-resistance of the MIV, the capacitor C MIV is the capacitor induced by the insulating wall of the MIV, and R I and R D are the input resistor and the divider resistor, respectively, provided in the test circuit; Assuming a relative change in resistance of η, for a fault-free MIV group, the minimum voltage V MIV_normal_min and the maximum voltage V MIV_normal_max at the test points are: (1) (2)。
  9. 9. the method of claim 8, wherein the voltage range corresponding to the fault-free MIV group is V MIV_normal_min ～V MIV_normal_max , considering that there is a process deviation in the actual resistance; judging whether the voltage of the test point is in a normal voltage range or not through a double-limit voltage comparator, wherein the setting requirement of the threshold voltage is V TH1 ≤V MIV_normal_min ,V TH2 ≥V MIV_normal_max ; If V TH1 ≤V MIV ≤V TH2 , the output signal V out is high, if V MIV ＜V TH1 or V MIV ＞V TH2 , the output signal V out is low, so the output signal V out is directly used to determine whether MIV is faulty.
  10. 10. The method of claim 9, wherein the single type of MIV fault detectable by the method satisfies the condition that for an MIV open circuit fault, a maximum value V MIV_open_max of the test point voltage in the open circuit state is less than a minimum value V MIV_normal_min of the test point voltage in the no fault state, and for an MIV short circuit fault, a minimum value V MIV_short_min of the test point voltage in the short circuit state is greater than a maximum value V MIV_normal_max of the test point voltage in the no fault state; for an MIV leakage fault, the maximum value V MIV_leak_max of the test point voltage in the leakage state is less than the minimum value V MIV_normal_min of the test point voltage in the no-fault state, (3) (4) (5) Wherein R parallel1 ,R parallel2 and R parallel3 are each represented as follows: (6) (7) (8)。

Description

MIV test circuit and test method based on voltage divider Technical Field The invention belongs to the field of test circuits, and particularly relates to an MIV test circuit and a test method based on a voltage divider. Background Three-dimensional integration technology is a promising solution to extend moore's law. Today's three-dimensional integrated circuits are mainly implemented by Through-Silicon Via (TSV), which has a higher integration density and lower power consumption than conventional two-dimensional integrated circuits. However, the volume of TSVs and the high requirements of the fabrication process limit further improvements in device integration. To overcome the above limitations, monolithic three-dimensional integration techniques have evolved. In monolithic three-dimensional integrated circuits (Monolithic Three-dimensional Integrated Circuit, M3D ICs), transistors are fabricated layer by layer on the same wafer, which eliminates the need for any die alignment, greatly reducing the size of the monolithic inter-layer vias (Monolithic Inter-tier Via, MIV). Although monolithic three-dimensional integration techniques can significantly reduce chip area and improve circuit performance, the high integration density and significant reduction in interlayer dielectric thickness make MIV very prone to defects. Related studies have shown that the yield of MIV is much lower than that of conventional through holes. As a hub for the electrical transmission of adjacent layers, MIV failure may lead to disruption of the signal integrity of the entire chip. Thus, MIV testing is critical for large-scale applications that implement M3D ICs. However, the existing MIV test circuit can only perform open-circuit and short-circuit tests, has a limited detectable fault range, and cannot meet the actual use requirements. Disclosure of Invention The invention provides an MIV test circuit and a test method based on a voltage divider, which are used for solving the problem that the prior art has a limited fault detection range. The invention is realized by the following technical scheme: a voltage divider-based MIV test circuit comprising a common test unit, a voltage dividing unit and a voltage comparing unit; The public test unit is used for switching different test modes so as to detect whether an open circuit fault, a short circuit fault or a leakage fault exists in the MIV; The voltage dividing unit is used for establishing a test model of the MIV group; the voltage comparison unit is used for judging whether the voltage of the test point is in a normal voltage range or not; The public test unit is connected with the voltage comparison unit through the voltage division unit. The MIV test circuit based on the voltage divider is characterized in that the common test unit is connected with a voltage dividing unit, and the voltage dividing unit is connected with a voltage comparison unit; the public test unit 1 comprises a test controller, a first test special MIV, a second test special MIV and a third test special MIV, wherein the first test special MIV, the second test special MIV and the third test special MIV are all arranged on a middle chip, and the test controller is arranged on an upper chip; the voltage division unit 2 comprises an upper chip voltage division unit 2 and a lower chip voltage division unit 2; One output end of the test controller is connected with the address input end of the multiplexer of the voltage division unit 2 in the upper chip, and the address input end of the multiplexer of the voltage division unit 2 in the lower chip is connected with the other output end of the test controller through a special MIV; After the first test special MIV, the second test special MIV and the third test special MIV are connected in parallel, one end connected with the upper chip is the MIV head end, and one end connected with the lower chip is the MIV tail end; The first ends of the first special MIV, the second special MIV and the third special MIV are connected with two output ends of the test controller, and the tail ends of the first special MIV, the second special MIV and the third special MIV are connected with address input ends of multiplexers in the lower chip. A voltage divider-based MIV test circuit, the voltage dividing unit 2 includes a one-out-of-two multiplexer, an i-th one-out-of-four multiplexer, an i-th input resistor R I1_i, an i-th input resistor R I2_i, a voltage dividing resistor R D1, and a voltage dividing resistor R D2; The input end 0 of the alternative multiplexer 22 is connected with one end of the divider resistor R D1, the input end 1 of the alternative multiplexer is connected with one end of the divider resistor R D2, and the output end of the alternative multiplexer is connected with the ground. The MIV test circuit based on the voltage divider comprises a voltage divider unit 2, wherein the input end 0 of the first four-way multiplexer is connected with a power supply, th