CN-116486880-B - Method for detecting memory

Abstract

The embodiment of the disclosure provides a detection method of a memory, which relates to the technical field of semiconductors and comprises the steps of writing first storage data into all storage units of the memory, sequentially reading the first storage data of each storage unit according to a first reading sequence, and then writing second storage data back to the storage unit, so that when the storage data of adjacent storage units are different, the precharge time of bit lines and reference bit lines connected with the storage units is shortened, and if the storage data of the next storage unit is different from the first storage data, the first preset time when errors are proved to be the precharge time corresponding to the memory, and therefore, the precharge time of different memories can be tested to divide the advantages and disadvantages of the memory.

Inventors

• CHU XIKUN

Assignees

• 长鑫存储技术有限公司

Dates

Publication Date

20260508

Application Date

20220114

Claims (16)

1. 1. A method for detecting a memory, wherein the memory includes a plurality of memory banks, each of the memory banks including a plurality of memory cells arranged in a rectangular array, the method comprising the steps of: Step a, writing first storage data into all storage units of the memory; And b, reading first storage data of each storage unit according to a first reading sequence, writing second storage data into each storage unit after each storage unit is read, wherein the second storage data is different from the first storage data, precharging a bit line connected with the storage unit and a reference bit line for a first preset time, wherein the first preset time is less than the precharge time, and then reading storage data of a next storage unit, and judging whether the read storage data of the next storage unit is identical to the first storage data.
2. 2. The method of detecting a memory according to claim 1, wherein after the step of reading the first stored data of each of the memory cells in the first reading order, the method further comprises: step c, reading second storage data of each storage unit according to a second reading sequence, writing first storage data into each storage unit after each storage unit is read, and precharging the bit line and the reference bit line which are connected with the storage unit for a first preset time, wherein the first preset time is smaller than the precharge time, then reading storage data of a next storage unit, and judging whether the read storage data of the next storage unit is identical to the second storage data; wherein the second read order is opposite to the first read order.
3. 3. The method for detecting a memory according to claim 2, wherein after step c, the method further comprises: And (c) if the storage data of the next storage unit is the same as the first storage data in the first reading sequence, and if the storage data of the next storage unit is the same as the second storage data in the second reading sequence, gradually shortening the value of the first preset time in the step b, and repeating the step b and the step c until the storage data of the next storage unit is different from the first storage data in the first reading sequence, or the storage data of the next storage unit is different from the second storage data in the second reading sequence.
4. 4. The method according to any one of claims 1-3, wherein after step a, before step b, the method further comprises reducing the equalization voltage of the memory.
5. 5. A method of testing a memory according to any one of claims 1-3, wherein after step a, before step b, the method further comprises: And writing a first voltage to each memory bank, wherein the first voltage is smaller than the starting voltage of a word line in the memory bank.
6. 6. The method of claim 5, wherein a second voltage is written to each of the banks, the second voltage being greater than a turn-off voltage of a transistor connected to a word line in the bank.
7. 7. The method of detecting a memory according to claim 4, wherein the memory further comprises an equalizer unit provided between the bit line and the reference bit line; the equalization voltage is applied to the bit line and the reference bit line by the equalizer unit.
8. 8. The method of detecting a memory according to claim 7, wherein the equalizer unit includes a first transistor, a second transistor, and a third transistor; the grid electrode of the first transistor, the grid electrode of the second transistor and the grid electrode of the third transistor are connected; The source electrode of the first transistor is connected with the bit line, and the drain electrode of the first transistor is connected with the reference bit line; The source electrode of the second transistor is connected with the bit line, and the drain electrode of the second transistor is connected with the source electrode of the third transistor; the drain of the third transistor is connected to the reference bit line.
9. 9. The method according to claim 8, wherein the equalizer unit further includes a first signal line connected to the gate of the first transistor, the gate of the second transistor, and the gate of the third transistor, respectively, the first signal line being configured to supply a voltage to the equalizer unit to turn on or off the equalizer unit.
10. 10. The method of detecting a memory according to claim 9, wherein a drain of the second transistor and a source of the third transistor are further connected to a second signal line for supplying a reset voltage to the bit line and the reference bit line.
11. 11. A method of testing a memory according to any one of claims 1 to 3, wherein the memory comprises a read circuit and a peripheral circuit, the read circuit being coupled to the bit line for transferring stored data coupled to the bit line into the peripheral circuit.
12. 12. The method for detecting a memory according to claim 11, wherein the reading circuit includes a reading transistor, a gate of which is connected to a third signal line for controlling on or off of the reading transistor; The source of the read transistor is connected with the bit line, and the drain of the read transistor is connected with the peripheral circuit.
13. 13. The method according to claim 12, wherein a drain of the read transistor is connected to the peripheral circuit through a fourth signal line.
14. 14. A method of detecting a memory according to any one of claims 1 to 3, further comprising a sense amplifier provided between the bit line and the reference bit line corresponding to the bit line for amplifying a voltage difference between the bit line and the reference bit line corresponding to the bit line.
15. 15. The method of detecting a memory according to claim 14, wherein the sense amplifier includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; The grid electrode of the fourth transistor is connected with the reference bit line, and the source electrode of the fourth transistor is connected with the bit line; The grid electrode of the fifth transistor is connected with the bit line, the source electrode of the fifth transistor is connected with the reference bit line, the drain electrode of the fifth transistor is connected with the drain electrode of the fourth transistor and is connected with a first power line, and the first power line is used for providing low potential voltage; a grid electrode of the sixth transistor is connected with the reference bit line, and a source electrode of the sixth transistor is connected with the bit line; the gate of the seventh transistor is connected to the bit line, the source of the seventh transistor is connected to the reference bit line, the drain of the seventh transistor is connected to the drain of the sixth transistor, and is connected to a second power line for providing a high potential voltage.
16. 16. The method of claim 15, wherein the fourth transistor and the fifth transistor are each N-type transistors, and the sixth transistor and the seventh transistor are each P-type transistors.

Description

Method for detecting memory Technical Field The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a detection method of a memory. Background In a dynamic random access memory (Dynamic random access memory, DRAM for short), a memory array is composed of a plurality of banks (banks) each of which is composed of a plurality of repeated memory cells (cells), when it is required to read memory data in the memory cells, address selection of the memory cells (cells) is first required to be completed, that is, one of the word lines is usually selected to activate the one word line, then a voltage difference between the bit line and a reference bit line is amplified by a Sense Amplifier (SA) by opening the bit line connected to the memory cells on the one word line at the same time, and the voltage difference is transferred to an IO line to complete a read operation of the memory, and before the other word line is opened after the word line is closed, precharge operation is required to be performed on the bit line and the reference bit line so that the potential of the bit line and the reference bit line return to the same reference value to ensure the authenticity of the memory data of the memory cells connected to the other bit line, therefore, the size of precharge time directly affects the quality of the memory, but the related art does not have an effective precharge time to detect the memory. Disclosure of Invention In view of the foregoing, embodiments of the present disclosure provide a method for detecting a memory, for testing a precharge time of the memory. The embodiment of the disclosure provides a detection method of a memory, the memory comprises a plurality of memory banks, each memory bank comprises a plurality of memory cells arranged in a rectangular array, wherein the detection method comprises the following steps: Step a, writing first storage data into all storage units of the memory; And b, reading first storage data of each storage unit according to a first reading sequence, writing second storage data into each storage unit after each storage unit is read, wherein the second storage data is different from the first storage data, precharging the bit line connected with the storage unit and the reference bit line for a first preset time, wherein the first preset time is smaller than the precharge time, then reading storage data of a next storage unit, and judging whether the read storage data of the next storage unit is identical to the first storage data. In some embodiments, after the step of reading the first stored data of each of the memory cells in the first read order, the method further comprises: Step c, reading second storage data of each storage unit according to a second reading sequence, writing first storage data into each storage unit after each storage unit is read, and precharging the bit line and the reference bit line which are connected with the storage unit for a first preset time, wherein the first preset time is smaller than the precharge time, then reading storage data of a next storage unit, and judging whether the read storage data of the next storage unit is identical to the second storage data; wherein the second read order is opposite to the first read order. In some embodiments, after step c, the method further comprises: And if the storage data of the next storage unit is the same as the first storage data when the storage data is read according to the first reading sequence, and if the storage data of the next storage unit is the same as the second storage data when the storage data is read according to the second reading sequence, gradually shortening the numerical value of the first preset time in the step b, and repeating the step b and the step c until the storage data of the next storage unit is different from the first storage data when the storage data is read according to the first reading sequence or the storage data of the next storage unit is different from the second storage data when the storage data is read according to the second reading sequence. In some embodiments, after step a, the method of detecting further comprises reducing an equilibration voltage of the memory before step b. In some embodiments, after step a, the method of detecting further comprises, before step b, writing a first voltage to each of the memory banks, the first voltage being less than an on voltage of a word line in the memory bank. In some embodiments, a second voltage is written to each of the memory banks, the second voltage being greater than a turn-off voltage of a transistor connected to a word line in the memory bank. In some embodiments, the memory further comprises an equalizer unit disposed between the bit line and the reference bit line; the equalization voltage is applied to the bit line and the reference bit line by the equalizer unit. In some embodiments, the equalizer unit includes a first transistor, a second