CN-116505759-B - Voltage-adjustable charge pump circuit and equipment

CN116505759BCN 116505759 BCN116505759 BCN 116505759BCN-116505759-B

Abstract

The application provides a charge pump circuit and equipment capable of adjusting voltage, wherein the circuit comprises a voltage doubling module, a voltage boosting module and a voltage output module, the voltage doubling module, the voltage boosting module and the voltage output module are all connected with a clock module, the voltage doubling module is connected with the voltage boosting module, the voltage doubling module generates a voltage doubling signal based on the clock signal and outputs the voltage doubling signal to the voltage boosting module, the voltage boosting module generates a voltage boosting signal according to the clock signal and the voltage doubling signal and outputs the voltage boosting signal to the voltage output module, and the voltage output module generates an output signal according to the clock signal and the voltage boosting signal. The application has the effects that the circuit output signal has a larger voltage range, and the adjusting range of the circuit output signal has more flexibility.

Inventors

CHEN YANG
LIU SHUKAI
CHEN ZHIMING

Assignees

长沙泰科阳微电子有限公司

Dates

Publication Date: 20260505
Application Date: 20230316

Claims (2)

1. The circuit comprises a clock module for providing a clock signal, and is characterized by further comprising a voltage doubling module, a voltage boosting module and a voltage output module, wherein the voltage doubling module, the voltage boosting module and the voltage output module are all connected with the clock module, the voltage doubling module is connected with the voltage boosting module, the voltage doubling module generates a voltage doubling signal based on the clock signal and outputs the voltage doubling signal to the voltage boosting module, the voltage boosting module generates a voltage boosting signal according to the clock signal and the voltage doubling signal and outputs the voltage boosting signal to the voltage output module, and the voltage output module generates an output signal according to the clock signal and the voltage boosting signal, and the voltage range of the output signal is larger than twice the voltage range of the clock signal; the voltage doubling module comprises a second voltage doubling charge pump unit and an inversion unit, the second voltage doubling charge pump unit is connected with the inversion unit, the inversion unit is connected with the pressurizing module, the second voltage doubling charge pump unit generates the voltage doubling signal based on the clock signal, the inversion unit performs inversion processing on the voltage doubling signal, and the voltage doubling signal after the inversion processing is output to the pressurizing module; The second voltage-multiplying charge pump unit comprises a capacitor C1, a capacitor C2, a PMOS tube M1 and a PMOS tube M2, wherein the capacitor C1 is connected with one end of the clock module, the capacitor C2 is connected with the other end of the clock module, the other end of the capacitor C1 is connected with the drain electrode of the PMOS tube M1 and the grid electrode of the PMOS tube M2, the other end of the capacitor C2 is connected with the grid electrode of the PMOS tube M1 and the drain electrode of the PMOS tube M2, the drain electrode and the source electrode of the PMOS tube M2 and the source electrode of the PMOS tube M1 are connected with the inverting unit; the inverting unit comprises a PMOS tube M3, an NMOS tube M4, a PMOS tube M5, an NMOS tube M6, a PMOS tube M7 and an NMOS tube M8, wherein sources of the PMOS tube M1, the PMOS tube M2, the PMOS tube M3, the PMOS tube M5 and the PMOS tube M7 are connected in series, drains of the PMOS tube M2 are connected with gates of the PMOS tube M3 and the NMOS tube M4, drains of the PMOS tube M3 and the NMOS tube M4 are connected with gates of the PMOS tube M5 and the NMOS tube M6, drains of the PMOS tube M5 and the NMOS tube M6 are connected with gates of the PMOS tube M7 and the NMOS tube M8, drains of the PMOS tube M7 and the NMOS tube M8, and sources of the NMOS tube M4, the NMOS tube M6 and the NMOS tube M8 are connected with the pressurizing module; the voltage boosting module comprises a PMOS tube M1 and an NMOS tube M2, a first reference voltage is input to the grid electrode of the PMOS tube M1, a second reference voltage is input to the grid electrode of the NMOS tube M2, the drain electrodes of the PMOS tube M7 and the NMOS tube M8 are connected with the source electrode of the PMOS tube M1, the source electrodes of the NMOS tube M4, the NMOS tube M6 and the NMOS tube M8 are connected with the source electrode of the NMOS tube M2, the source electrode of the NMOS tube M2 is also connected with one end of the clock module, and the drain electrodes of the PMOS tube M1 and the NMOS tube M2 are connected with the voltage output module; The voltage output module comprises a capacitor c1, a capacitor c2, an NMOS tube m3 and an NMOS tube m4, wherein the PMOS tube m1 and the drain electrode of the NMOS tube m2 are connected with one end of the capacitor c1, the other end of the capacitor c1 is connected with the source electrode of the NMOS tube m3 and the grid electrode of the NMOS tube m4, one end of the capacitor c2 is connected with one end of the clock module, the other end of the capacitor c2 is connected with the grid electrode of the NMOS tube m3 and the source electrode of the NMOS tube m4, the drain electrode of the NMOS tube m3 is connected with the drain electrode of the NMOS tube m4, and the grid electrode of the NMOS tube m4 is used for outputting the output signal.
2. An apparatus comprising a voltage-adjustable charge pump circuit of claim 1.

Description

Voltage-adjustable charge pump circuit and equipment The application relates to a Chinese patent application (application number 202310254947.4, application day 2023, month 03 and 16, and the name of the application is charge pump circuit and device capable of adjusting voltage). Technical Field The invention belongs to the technical field of charge pumps, and particularly relates to a voltage-adjustable charge pump circuit and equipment. Background As processes progress, system applications move closer to lower supply voltages and circuit and system designs migrate to deep submicron, typically the supply voltage decreases to 1.5V or less under such processes. Because in many low supply voltage and switched capacitor systems high voltages are required to drive the analog switches. A charge pump loop is required to obtain a DC voltage higher than the supply voltage. In the related art, a conventional multiplication charge pump is generally used to obtain a DC voltage higher than a power supply voltage, and the conventional multiplication charge pump includes a clock circuit for generating an alternate clock signal, two capacitors for filtering, and two NMOS transistors. Furthermore, since the charge pump circuit is an active circuit, its output is affected by input terminal parameters (e.g., capacitance, resistance, etc.) and input voltage. Since these parameters are fixed, the output voltage regulation range of the charge pump circuit is limited. Disclosure of Invention The invention provides a charge pump circuit and a charge pump device with adjustable voltage. In a first aspect, the invention provides a charge pump circuit capable of adjusting voltage, the circuit comprises a clock module for providing a clock signal, the circuit further comprises a voltage doubling module, a voltage boosting module and a voltage output module, the voltage doubling module, the voltage boosting module and the voltage output module are all connected with the clock module, the voltage doubling module is connected with the voltage boosting module, the voltage doubling module generates a voltage doubling signal based on the clock signal and outputs the voltage doubling signal to the voltage boosting module, the voltage boosting module generates a voltage boosting signal according to the clock signal and the voltage doubling signal and outputs the voltage boosting signal to the voltage output module, and the voltage output module generates an output signal according to the clock signal and the voltage boosting signal, and the voltage range of the output signal is larger than twice the voltage range of the clock signal. Optionally, the voltage doubling module includes a first voltage doubling charge pump unit and a voltage doubling auxiliary unit, the first voltage doubling charge pump unit is connected with the voltage doubling auxiliary unit, the voltage doubling auxiliary unit is connected with the pressurizing module, the first voltage doubling charge pump unit and the voltage doubling auxiliary unit generate the voltage doubling signal based on the clock signal, and the voltage doubling auxiliary unit outputs the voltage doubling signal to the pressurizing module. Optionally, the first voltage-multiplying charge pump unit includes a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, an NMOS tube M1, an NMOS tube M2, an NMOS tube M3, and an NMOS tube M4, one ends of the capacitor C1 and the capacitor C4 are all connected with one end of the clock module, one ends of the capacitor C2 and the capacitor C3 are all connected with the other end of the clock module, the other end of the capacitor C1 is connected with the source of the NMOS tube M1 and the gate of the NMOS tube M2, the other end of the capacitor C2 is connected with the gate of the NMOS tube M1 and the source of the NMOS tube M2, the other end of the capacitor C3 is connected with the source of the NMOS tube M3 and the gate of the NMOS tube M4, the other end of the capacitor C4 is connected with the gate of the NMOS tube M3 and the source of the NMOS tube M4, the drain of the NMOS tube M2 and the drain of the NMOS tube M3 and the drain of the NMOS tube M4 are all connected with the auxiliary voltage-multiplying unit. Optionally, the voltage doubling auxiliary unit includes a capacitor C5, a capacitor C6, an NMOS tube M5 and an NMOS tube M6, a gate of the NMOS tube M5 is connected with a gate of the NMOS tube M4, a gate of the NMOS tube M6 is connected with a gate of the NMOS tube M2, the NMOS tube M1, the NMOS tube M2, the NMOS tube M3, the NMOS tube M4, the NMOS tube M5 and a drain of the NMOS tube M6 are connected in series, a source of the NMOS tube M5 is connected with one end of the capacitor C5 and the pressurizing module, a source of the NMOS tube M6 is connected with one end of the capacitor C6 and the pressurizing module, another end of the capacitor C5 is connected with one end of the clock module, and another end of the capacitor C6 is connec