CN-116522834-B - Time delay prediction method, device, equipment and storage medium

CN116522834BCN 116522834 BCN116522834 BCN 116522834BCN-116522834-B

Abstract

The application discloses a time delay prediction method, a device, equipment and a storage medium, wherein the time delay prediction method comprises the steps of obtaining unit characteristic information of each unit in a circuit and a characteristic sequence of each unit interconnection line; the method comprises the steps of calculating an equivalent capacitance value of an interconnection line path between units based on capacitance values and resistance values of interconnection lines of the units, determining a target interconnection line time delay characteristic between the units based on the equivalent capacitance values, determining unit time delay characteristics of the units based on the equivalent capacitance values and unit characteristic information, inputting the interconnection line time delay characteristics and the unit time delay characteristics into a preset time delay prediction model, and performing prediction processing on the interconnection line time delay characteristics and the unit time delay characteristics based on the time delay prediction model to obtain a time delay result of the circuit. The application equalizes the capacitance value and the resistance value of each unit interconnection line into equivalent capacitance value, overcomes the defect that the load capacitance ignores the resistance shielding effect in the related technology, reduces the error of the load capacitance and improves the accuracy of time sequence prediction.

Inventors

TAO SIMIN
LIU HE
Long Shuaiying
XIE BIWEI
LI XINGQUAN

Assignees

鹏城实验室

Dates

Publication Date: 20260505
Application Date: 20230324

Claims (8)

1. A method of delay prediction, the method comprising: acquiring unit characteristic information of each unit in a circuit and a characteristic sequence of each unit interconnection line, wherein the characteristic sequence comprises a capacitance value and a resistance value; calculating an equivalent capacitance value of each inter-cell interconnect line path based on the capacitance value and the resistance value of each cell interconnect line, and determining a target interconnect line time delay characteristic between each cell based on the equivalent capacitance value; Determining the unit time delay characteristic of each unit based on the equivalent capacitance value and the unit characteristic information; Inputting the interconnection line time delay characteristics and the unit time delay characteristics into a preset time delay prediction model, and performing prediction processing on the interconnection line time delay characteristics and the unit time delay characteristics based on the time delay prediction model to obtain a time delay result of the circuit; the step of calculating an equivalent capacitance value of each inter-cell interconnect line path based on the capacitance value and the resistance value of each cell interconnect line, and determining a target interconnect line delay characteristic between each cell based on the equivalent capacitance value includes: establishing an RC tree model of each inter-cell interconnection line path based on the capacitance value and the resistance value of each cell interconnection line, and determining the resistance value of each node in the RC tree model; equivalent all nodes downstream of each node in the RC tree model to pi model of each node; Calculating an equivalent capacitance value of each inter-unit interconnection line path based on a pi model of each node; Based on the equivalent capacitance value of each node and the resistance value of each node, ECM time delay among the units is calculated; Determining the ECM latency as the target interconnect latency characteristic; after the step of calculating ECM delay between the units based on the equivalent capacitance value of each node and the resistance value of each node, the method includes: determining capacitance values of all nodes in the RC tree model; based on the resistance value and the capacitance value of each node, performing recursive calculation on the ECM time delay to obtain the second moment of each node; based on the ECM time delay and the second moment, calculating to obtain MD2M time delay among the units; The step of determining the ECM latency as the target interconnect latency characteristic includes: and determining the ECM delay and the MD2M delay as the target interconnection line delay characteristic.
2. The method of delay prediction of claim 1, wherein after the step of calculating an MD2M delay between each of the units based on the ECM delay and the second moment, the method comprises: Determining an Elmore time delay and a D2M time delay between the units based on the capacitance value and the resistance value of each unit interconnection line; and determining the ECM delay, the MD2M delay, the Elmore delay and the D2M delay as target interconnection line delay characteristics among the units.
3. The method for predicting delay as claimed in claim 1, wherein, before the step of inputting the interconnect line delay feature and the unit delay feature into a preset delay prediction model, performing prediction processing on the interconnect line delay feature and the unit delay feature based on the delay prediction model to obtain the delay result of the circuit, the method comprises: obtaining a unit feature sample and a target time delay result label of the unit feature sample, wherein the unit feature sample comprises an interconnection line time delay feature sample and a unit time delay feature sample; and performing iterative training on a preset model to be trained based on the interconnection line time delay feature sample, the unit time delay feature sample and the target time delay result label of the unit time delay feature sample to obtain a time delay prediction model meeting the precision condition.
4. The method of delay prediction of claim 3, wherein the step of obtaining a target delay result tag for the unit feature sample comprises: Obtaining a target interconnection line time delay characteristic, a unit time delay characteristic and an initial time delay result value of the unit characteristic sample; And summing the target interconnection line time delay characteristic and the unit time delay characteristic of the unit characteristic sample to obtain a target time delay result value of the unit characteristic sample, and calculating the ratio of the initial time delay result value to the target time delay result value of the unit characteristic sample to obtain a target time delay result label of the unit characteristic sample.
5. The method for predicting delay as claimed in claim 3, wherein the step of iteratively training a preset model to be trained based on the interconnect line delay feature sample, the unit delay feature sample and the target delay result label of the unit delay feature sample to obtain the delay prediction model satisfying the accuracy condition comprises: Inputting the interconnection line time delay characteristic sample and the unit time delay characteristic sample into the preset model to be trained to obtain a predicted time delay result; Performing difference calculation on the predicted time delay result and a target time delay result label of the unit feature sample to obtain an error result; judging whether the error result meets an error standard indicated by a preset error threshold range; And if the error result does not meet the error standard indicated by the preset error threshold range, returning to the step of inputting the interconnection line time delay characteristic sample and the unit time delay characteristic sample into the preset model to be trained to obtain a predicted time delay result, and stopping training until the training error result meets the error standard indicated by the preset error threshold range to obtain the time delay prediction model meeting the accuracy condition.
6. A delay predicting apparatus, characterized in that the delay predicting apparatus comprises: The device comprises an acquisition module, a control module and a control module, wherein the acquisition module is used for acquiring unit characteristic information of each unit in a circuit and a characteristic sequence of each unit interconnection line, and the characteristic sequence comprises a capacitance value and a resistance value; The calculation module is used for calculating the equivalent capacitance value of each inter-unit interconnection line path based on the capacitance value and the resistance value of each unit interconnection line and determining the target interconnection line time delay characteristic between each unit based on the equivalent capacitance value; the determining module is used for determining the unit time delay characteristics of each unit based on the equivalent capacitance value and the unit characteristic information; The prediction module is used for inputting the interconnection line delay characteristics and the unit delay characteristics into a preset delay prediction model, and performing prediction processing on the interconnection line delay characteristics and the unit delay characteristics based on the delay prediction model to obtain a delay result of the circuit; wherein the computing module comprises: The establishing module is used for establishing an RC tree model of each inter-unit interconnection line path based on the capacitance value and the resistance value of each unit interconnection line and determining the resistance value of each node in the RC tree model; the equivalent module is used for equivalent all the nodes downstream of each node in the RC tree model to be pi models of each node; the equivalent capacitance value calculation module is used for calculating the equivalent capacitance value of the inter-unit interconnection line paths based on the pi model of each node; the ECM time delay calculation module is used for calculating ECM time delay among the units based on the equivalent capacitance value of each node and the resistance value of each node; a first determining module configured to determine the ECM latency as the target interconnect latency characteristic; the computing module further includes: The capacitance value determining module is used for determining capacitance values of all nodes in the RC tree model; The recursive computation module is used for carrying out recursive computation on the ECM time delay based on the resistance value and the capacitance value of each node to obtain the second moment of each node; the MD2M time delay calculation module is used for calculating and obtaining MD2M time delay among the units based on the ECM time delay and the second moment; A second determining module, configured to determine the ECM latency and the MD2M latency as the target interconnect line latency characteristics.
7. A delay predicting device is characterized by comprising a memory, a processor and a program stored on the memory for realizing the delay predicting method, The memory is used for storing a program for realizing the time delay prediction method; the processor is configured to execute a program implementing the delay prediction method to implement the steps of the delay prediction method according to any one of claims 1 to 5.
8. A storage medium having stored thereon a program for implementing a delay prediction method, the program for implementing the delay prediction method being executed by a processor to implement the steps of the delay prediction method according to any one of claims 1 to 5.

Description

Time delay prediction method, device, equipment and storage medium Technical Field The present application relates to the field of electronic design automation technology, and in particular, to a method, an apparatus, a device, and a storage medium for predicting time delay. Background For the design timing convergence of high performance chips, in order to obtain a chip design with accurate timing, a timing analysis tool needs to be called to analyze the timing margin at each stage of the physical design, so as to guide the chip design process. Therefore, accurate timing analysis results are important for iterative optimization of chip-guided design and obtaining better timing convergence results. The related art uses a traditional algorithm in a time sequence estimation method after wiring a digital integrated circuit, wherein the time delay value of an interconnection line is calculated by using an Elmore model and a D2M model, and the load capacitance value of the downstream of each node needs to be calculated when the Elmore model and the D2M model are applied. However, there is a certain error in the sum of the ground capacitances, and the continuous accumulation of the error in the transfer process results in low accuracy of the timing prediction. Disclosure of Invention The application mainly aims to provide a time delay prediction method, a time delay prediction device and a storage medium, and aims to solve the technical problem of low accuracy of time sequence prediction in the prior art. In order to achieve the above object, the present application provides a delay prediction method, including: acquiring unit characteristic information of each unit in a circuit and a characteristic sequence of each unit interconnection line, wherein the characteristic sequence comprises a capacitance value and a resistance value; calculating an equivalent capacitance value of each inter-cell interconnect line path based on the capacitance value and the resistance value of each cell interconnect line, and determining a target interconnect line time delay characteristic between each cell based on the equivalent capacitance value; Determining the unit time delay characteristic of each unit based on the equivalent capacitance value and the unit characteristic information; inputting the interconnection line time delay characteristics and the unit time delay characteristics into a preset time delay prediction model, and performing prediction processing on the interconnection line time delay characteristics and the unit time delay characteristics based on the time delay prediction model to obtain a time delay result of the circuit. Optionally, the step of calculating an equivalent capacitance value of each inter-cell interconnect line path based on the capacitance value and the resistance value of each cell interconnect line, and determining a target interconnect line delay characteristic between each cell based on the equivalent capacitance value includes: establishing an RC tree model of each inter-cell interconnection line path based on the capacitance value and the resistance value of each cell interconnection line, and determining the resistance value of each node in the RC tree model; equivalent all nodes downstream of each node in the RC tree model to pi model of each node; Calculating an equivalent capacitance value of each inter-unit interconnection line path based on a pi model of each node; Based on the equivalent capacitance value of each node and the resistance value of each node, ECM time delay among the units is calculated; the ECM latency is determined as the target interconnect latency characteristic. Optionally, after the step of calculating ECM delay between the units based on the equivalent capacitance value of each node and the resistance value of each node, the method includes: determining capacitance values of all nodes in the RC tree model; based on the resistance value and the capacitance value of each node, performing recursive calculation on the ECM time delay to obtain the second moment of each node; based on the ECM time delay and the second moment, calculating to obtain MD2M time delay among the units; The step of determining the ECM latency as the target interconnect latency characteristic includes: and determining the ECM delay and the MD2M delay as the target interconnection line delay characteristic. Optionally, after the step of calculating the MD2M delay between the units based on the ECM delay and the second moment, the method includes: Determining an Elmore time delay and a D2M time delay between the units based on the capacitance value and the resistance value of each unit interconnection line; and determining the ECM delay, the MD2M delay, the Elmore delay and the D2M delay as target interconnection line delay characteristics among the units. Optionally, the step of inputting the interconnect line delay feature and the unit delay feature to a preset delay prediction model, and pe