CN-116523006-B - Data processing system, method of operating the same, and computing system using the same

Abstract

The present disclosure relates to a data processing system that may include a matrix splitting circuit configured to split a matrix into a positive matrix and a negative matrix and store the positive matrix and the negative matrix in a first sub-array and a second sub-array within a computation memory, respectively, a vector conversion circuit configured to generate an offset vector by adding elements within a vector to an offset for converting a negative element having a largest absolute value among the elements of the vector to a zero element or a positive element and applying the offset vector to a row line of the first sub-array and the second sub-array, and an offset correction circuit configured to generate an offset correction value by subtracting a result of multiplying the offset by the positive matrix from a result of multiplying the offset by the negative matrix and subtracting the offset correction value from a computation value output by the first sub-array and the second sub-array.

Inventors

• Zhu Xiangyin

Assignees

• 爱思开海力士有限公司

Dates

Publication Date

20260505

Application Date

20220913

Priority Date

20220120

Claims (19)

1. 1. A data processing system, comprising: a computational memory comprising one or more sub-arrays, each sub-array comprising a plurality of memory cells coupled between a plurality of row lines and a plurality of column lines; Matrix splitting circuit: When a negative element is included in a matrix received from a host device, splitting the matrix into a positive matrix composed of positive elements of the matrix and a negative matrix composed of absolute values of the negative elements of the matrix, and Storing the positive matrix and the negative matrix in a first sub-array and a second sub-array, respectively, within the computational memory; Vector conversion circuit: when a negative element is included in a vector received from the host device, generating an offset vector by adding elements within the vector to an offset for converting a negative element having the largest absolute value among elements of the vector to a zero element or a positive element, and Applying the offset vector to row lines of the first and second sub-arrays, and Offset correction circuit: Generating an offset correction value by subtracting the result of multiplying the offset by the negative matrix from the result of multiplying the offset by the positive matrix, and The offset correction value is subtracted from the calculated values output from the first sub-array and the second sub-array.
2. 2. The data processing system of claim 1, wherein the computation memory generates the computation value by subtracting a negative computation value from a positive computation value, the positive computation value being output from the first sub-array as a result of multiplication of the positive matrix and the offset vector, the negative computation value being output from the second sub-array as a result of multiplication of the negative matrix and the offset vector.
3. 3. The data processing system of claim 2, wherein the computing memory further comprises: An analog-to-digital converter for converting the positive and negative calculated values into digitized positive and negative calculated values, respectively, and A digital subtractor subtracting the digitized negative calculation value from the digitized positive calculation value to generate the calculation value.
4. 4. The data processing system of claim 2, wherein the computing memory further comprises: an analog subtractor subtracting the negative calculated value from the positive calculated value, and An analog-to-digital converter converts an output of the analog subtractor to generate the calculated value.
5. 5. The data processing system of claim 1, Wherein each element constituting the offset vector is a binary number consisting of a plurality of bits, The data processing system further includes an offset vector splitting circuit that: Generating a sequential vector comprising one or more partial offset vectors by bit-wise splitting the offset vector according to bit values, and The vector conversion circuit sequentially applies the partial offset vector to row lines of the first and second sub-arrays.
6. 6. The data processing system of claim 5, wherein the computational memory further comprises a bit value ordering circuit, the bit value ordering circuit: sorting a part of positive calculated values as a result of multiplication of the partial offset vector with the positive matrix according to bit values of the partial offset vector, Sorting the partial negative calculated values as a result of the multiplication of the partial offset vector with the negative matrix according to the bit values of the partial offset vector, Obtaining a positive calculation value by summing all ordered partial positive calculation values, and The negative calculation is obtained by summing all ordered partial negative calculation values.
7. 7. A method of operation of a data processing system, comprising: Providing a computation memory comprising one or more subarrays, each subarray comprising a plurality of memory cells coupled between a plurality of row lines and a plurality of column lines; when a negative element is included in a matrix received from a host device, splitting the matrix into a positive matrix composed of positive elements of the matrix and a negative matrix composed of absolute values of the negative elements of the matrix by a negative number calculation control circuit; storing the positive matrix and the negative matrix in a first sub-array and a second sub-array, respectively, within the computational memory; When a negative element is included in a vector received from the host device, adding, by the negative number calculation control circuit, an element within the vector to an offset for converting a negative element having the largest absolute value among elements within the vector to a zero element or a positive element; The negative calculation control circuit applies the offset vector to row lines of the first and second subarrays; The negative calculation control circuit generates an offset correction value by subtracting the result of multiplying the offset by the negative matrix from the result of multiplying the offset by the positive matrix, and The negative calculation control circuit subtracts the offset correction value from calculated values output from the first sub-array and the second sub-array.
8. 8. The method of operation of claim 7, further comprising generating the calculated value by subtracting a negative calculated value from a positive calculated value, the positive calculated value being output from the first sub-array as a result of multiplication of the positive matrix and the offset vector, the negative calculated value being output from the second sub-array as a result of multiplication of the negative matrix and the offset vector.
9. 9. The method of operation of claim 8, wherein the generating of the calculated value comprises: The calculation memory converting the positive calculation value and the negative calculation value into a digitized positive calculation value and a digitized negative calculation value, respectively, and The calculation memory subtracts the digitized positive calculation value from the digitized negative calculation value to generate the calculation value.
10. 10. The method of operation of claim 8, wherein the generating of the calculated value comprises: Subtracting the negative calculated value from the positive calculated value, and The calculated value is generated by converting the output of the analog subtractor into a digital value.
11. 11. The method of operation according to claim 7, Wherein each element constituting the offset vector is a binary number consisting of a plurality of bits, Wherein applying the offset vector comprises: Generating a sequential vector comprising one or more partial offset vectors by bit-wise splitting the offset vector according to bit values, and The partial offset vector is sequentially applied to row lines of the first and second sub-arrays.
12. 12. The method of operation of claim 11, further comprising: sorting a part of positive calculated values as a result of multiplication of the partial offset vector with the positive matrix according to bit values of the partial offset vector, Sorting the partial negative calculated values as a result of the multiplication of the partial offset vector with the negative matrix according to the bit values of the partial offset vector, Obtaining a positive calculation value by summing all ordered partial positive calculation values, and The negative calculation is obtained by summing all ordered partial negative calculation values.
13. 13. A computing system, comprising: a host device; a data processing system for processing a computation of an application in accordance with a request of the host device and comprising a computation memory including one or more subarrays, each subarray comprising a plurality of memory cells coupled between a plurality of row lines and a plurality of column lines, and Negative number calculation control circuit: Splitting a matrix received from the host device into a positive matrix and a negative matrix when the matrix includes negative elements therein; Generating an offset vector by adding the vector to an offset when a negative element is included in a vector received from the host device, and According to an offset correction value generated based on the offset, a calculated value is corrected, which is output from the calculation memory as a result of multiplication of each of the positive matrix and the negative matrix with the offset vector.
14. 14. The computing system of claim 13, wherein the sub-array comprises: a first sub-array storing the positive matrix and receiving the offset vector through its row lines, and A second sub-array storing the negative matrix and receiving the offset vector through its row lines.
15. 15. The computing system of claim 13, wherein the negative calculation control circuit further generates the offset correction value by subtracting a result of multiplying the offset by the negative matrix from a result of multiplying the offset by the positive matrix.
16. 16. The computing system of claim 13, wherein the computation memory generates the computation value by subtracting a negative computation value from a positive computation value, the positive computation value being output from a first sub-array as a result of multiplication of the positive matrix and the offset vector, the negative computation value being output from a second sub-array as a result of multiplication of the negative matrix and the offset vector.
17. 17. The computing system of claim 13, wherein the negative calculation control circuit further subtracts the offset correction value from the calculated value.
18. 18. The computing system of claim 13, Wherein each element constituting the offset vector is a binary number consisting of a plurality of bits, Wherein the negative calculation control circuit further: Generating a sequential vector comprising one or more partial offset vectors by bit-wise splitting the offset vector according to bit values, and The partial offset vectors are sequentially applied to row lines of a subarray storing the positive matrix and the negative matrix, respectively.
19. 19. The computing system of claim 18, wherein the computing memory is further to: sorting a part of positive calculated values as a result of multiplication of the partial offset vector with the positive matrix according to bit values of the partial offset vector, Ordering partial negative calculation values as a result of multiplying the partial offset vector by the negative matrix according to bit values of the partial offset vector, and Subtracting the sorted partial negative calculation value from the sorted partial positive calculation value.

Description

Data processing system, method of operating the same, and computing system using the same Cross Reference to Related Applications The present application claims priority from korean patent application No. 10-2022-0008499 filed on 1 month 20 of 2022, which is incorporated herein by reference in its entirety. Technical Field Embodiments of the present disclosure relate generally to data processing technology and, more particularly, to a data processing system, a method of operating the same, and a computing system using the same. Background As the importance of Artificial Intelligence (AI) applications and big data analysis increases, there is an increasing interest in computing systems that can efficiently process big data. An artificial neural network is one way to implement AI. The computation performed by the AI application is mainly composed of vector matrix multiplication, and various methods are being studied to accurately compute a large amount of data at high speed. Disclosure of Invention In an embodiment of the present disclosure, a data processing system may include a computation memory including one or more sub-arrays, each sub-array including a plurality of memory cells coupled between a plurality of row lines and a plurality of column lines, a matrix splitting circuit configured to split a matrix into a positive matrix composed of positive elements of the matrix and a negative matrix composed of absolute values of negative elements of the matrix when the matrix received from a host apparatus includes the negative elements, and store the positive matrix and the negative matrix in a first sub-array and a second sub-array within the computation memory, respectively, a vector conversion circuit configured to generate an offset vector by adding an element within the vector to an offset for converting a negative element having a largest absolute value among the elements of the vector to a zero element or a positive element, and applying the offset vector to the row lines of the first sub-array and the second sub-array, and an offset correction circuit configured to generate an offset correction value from the first sub-array and a second sub-array by subtracting the offset multiplied result from the positive matrix and the negative matrix, respectively, when the negative element is included in the vector received from the host apparatus. In an embodiment of the present disclosure, a method of operating a data processing system may include providing a computation memory including one or more sub-arrays, each sub-array including a plurality of memory cells coupled between a plurality of row lines and a plurality of column lines, splitting the matrix into a positive matrix composed of positive elements of the matrix and a negative matrix composed of absolute values of the negative elements of the matrix by a negative number computation control circuit when the matrix received from a host device includes the negative elements, storing the positive matrix and the negative matrix in a first sub-array and a second sub-array within the computation memory, respectively, generating an offset vector by adding an element within the vector to an offset by the negative number computation control circuit, the offset vector being used to convert the negative element having a maximum absolute value among the elements within the vector to a zero element or a positive element, when the matrix received from the host device includes the negative elements, subtracting the offset to the negative matrix by the negative number computation control circuit, and subtracting the negative number computation control circuit from the first sub-array the negative number computation control circuit generates an offset correction value and subtracting the negative number from the sub-array. In an embodiment of the present disclosure, a computing system may include a host device, a data processing system configured to process a computation of an application according to a request of the host device, and include a computation memory including one or more subarrays each including a plurality of memory cells coupled between a plurality of row lines and a plurality of column lines, and a negative computation control circuit configured to split a matrix into a positive matrix and a negative matrix when a negative element is included in the matrix received from the host device, generate an offset vector by adding the vector to an offset when the negative element is included in the vector received from the host device, and correct a computation value output from the computation memory as a result of multiplying each of the positive matrix and the negative matrix by the offset vector according to an offset correction value generated based on the offset. In an embodiment of the present disclosure, a method of operation of a built-in memory computing device may include generating an offset vector comprising non-negative elements by adding an adj