CN-116559624-B - Chip testing method, system, device and storage medium

CN116559624BCN 116559624 BCN116559624 BCN 116559624BCN-116559624-B

Abstract

The application relates to the field of chip test and discloses a chip test method, a system, equipment and a storage medium, wherein the method comprises the steps of controlling the on or off of a relay to regulate and control the power-on time and the power-off time of a chip for a plurality of times; the relay is electrically connected with the toggle switch of the chip test board, the toggle switch is in a normally open state in the test process, the test log of each power-on of the chip is read in real time, and the chip state in the test process is obtained according to the read result of the test log so as to judge whether the test is continued or a statistical test result of the chip is generated. The method omits the operation of manual pulling switch by using the relay, greatly simplifies the testing step, controls the on or off of the relay, can improve the accuracy of the testing result, reads the log in real time, can immediately stop the testing once abnormality is found, generates the statistical result, lightens the burden of the tester, and greatly improves the testing efficiency and quality.

Inventors

SHI PENG
FAN XUANRONG
LIU QIHAO
LIU YANG
YAN GANG
YANG MAOHUI
CUI ZIHAO
SU DANDAN

Assignees

山东云海国创云计算装备产业创新中心有限公司

Dates

Publication Date: 20260505
Application Date: 20230511

Claims (5)

1. A method of testing a chip, comprising: setting the parameters to be counted to zero, opening a log file and a statistic file, and outputting a log file handle and a statistic file handle, wherein the parameters to be counted comprise the number of measured slices, the number of passes, the first abnormal constant, the probability abnormal constant and the probability abnormal time statistic array; when waiting for the opening time corresponding to the opening instruction, sending a closing instruction to the relay, controlling the closing of the relay, and waiting according to the set time after closing; The method comprises the steps of performing a single test state, namely, performing the operation of sending the opening command and the closing command to the relay in a circulating way, wherein the single test state comprises four steps of sequentially performing the steps of firstly sending the opening command to the relay, waiting according to the set opening time, sending the closing command to the relay in the third step, indexing an opening time array according to the number of circulating times, waiting according to the indexing time, and increasing the indexing time along with the increase of the number of circulating times; the test log of each power-on of the chip is read in real time, and the test log is generated when one chip test passes the power-on and power-off test which indicates that the chip is powered on for a plurality of times and has different waiting time continuously; judging whether the test log contains a section passing the test or a section with abnormal test, and obtaining a judgment result of the read log; judging whether the cycle times are greater than the set times or not to obtain a judging result of the cycle times; according to the judgment results of the reading logs and the cycle times, the chip state in the test process is obtained to judge whether to continue the test; The method comprises the steps of obtaining the state of a chip in a test process, and simultaneously, selecting to light a continuous test indicator lamp, an abnormal sign indicator lamp or a system fault indicator lamp, judging whether the chip is abnormal when the abnormal sign indicator lamp is lightened, if so, updating the first abnormal constant, if not, updating the probability abnormal constant, writing the cycle number into the probability abnormal time statistic array, and if not, judging that the chip test is passed and updating the passing number; If the test is not needed to be continued, creating a formatted character string, writing the tested number of the slices, the passing number, the first abnormal constant and the probability abnormal constant into the formatted character string according to a set format, using each element index in the probability abnormal time statistic array to turn off the time array, converting the time array into a character string, writing the character string into the formatted character string, and writing the finally obtained formatted character string into the statistic file to generate a statistical test result of the chip.
2. The chip testing method according to claim 1, further comprising: and controlling the front panel to display the chip state and the statistical test result in real time.
3. A chip testing system, comprising: The initialization module is used for setting the parameters to be counted to zero, opening the log file and the statistic file, and outputting a log file handle and a statistic file handle, wherein the parameters to be counted comprise the number of measured slices, the number of passing, the first abnormal constant, the probability abnormal constant and the probability abnormal time statistic array; The control switch module is used for sending an opening instruction to the relay and controlling the opening of the relay; the method comprises the steps of receiving a turn-on command from a relay, sending a turn-off command to the relay after waiting for the turn-on time corresponding to the turn-on command, controlling the turn-off of the relay, waiting for a set time after turning off, circularly executing the operation of sending the turn-on command and the turn-off command to the relay, and sequentially executing the four steps in a single test state, wherein the steps comprise firstly sending the turn-on command to the relay, waiting for the set turn-on time, sending the turn-off command to the relay in a third step, and using a cycle index turn-off time array to wait for the index time, wherein the index time is increased along with the increase of the cycle number; The log reading module is used for reading the test log of each power-on of the chip in real time, and the test log is generated each time when one chip test passes the power-on and power-off test which indicates that the chip is continuously powered on for multiple times and has different waiting time; the log reading module comprises a log judging unit, a number judging unit, a state obtaining unit and a test processing unit, wherein the log judging unit is used for judging whether a test log contains a section passing through the test or a section abnormal in the test to obtain a judging result of a read log, the number judging unit is used for judging whether the number of times of circulation is larger than a set number of times to obtain a judging result of the number of times of circulation, the state obtaining unit is used for obtaining the state of the chip in the test process according to the judging result of the read log and the number of times of circulation to judge whether to continue the test, the continuous test indicator lamp, the abnormal sign indicator lamp or the system fault indicator lamp is selected to be lighted while the state of the chip in the test is obtained, if the abnormal sign indicator lamp is lighted, whether the chip is abnormal in the first power-on state is judged, if the abnormal state is judged, the abnormal in the first power-on state is updated, the abnormal state is updated, if the abnormal state is updated, and the number of times of circulation is written into the abnormal time statistics array of the abnormal state is judged, if the chip is not the abnormal state is lighted, and the chip is passed through the test is judged; The result statistics module is used for generating a statistical test result of the chip when the log reading module judges that the test is not required to be continued, and comprises a character string creation unit used for creating a formatted character string, writing the tested number of the chips, the passing number, the first abnormal constant and the probability abnormal constant into the formatted character string according to a set format, a file writing unit used for indexing a turn-off time array by using each element in the probability abnormal time statistics array, converting the element into the character string, writing the character string into the formatted character string, and writing the finally obtained formatted character string into the statistics file.
4. A chip testing apparatus comprising a processor and a memory, wherein the processor implements the chip testing method of claim 1 or 2 when executing a computer program stored in the memory.
5. A computer readable storage medium for storing a computer program, wherein the computer program when executed by a processor implements the chip test method of claim 1 or 2.

Description

Chip testing method, system, device and storage medium Technical Field The present invention relates to the field of chip testing, and in particular, to a method, a system, an apparatus, and a storage medium for testing chips. Background Chip testing is used for detecting whether the function of a chip is correct, and most of chip testing currently requires self-design and building of a testing system. The self-built test system is more focused on the realization of a single test function, but the usability and the accuracy of the self-built test system can be ignored. Mechanical labor and statistics are generally required in the test process, and the test accuracy often depends on experience of a tester, so that the test efficiency is low. The power-on abnormality is that a certain module cannot work normally after power-on, and is a common chip fault, and needs to be carefully checked by a tester. There are many places where such faults may occur, and power-up anomalies may be caused by designs, layouts, lithography, packaging, and even firmware. The probability power-on abnormality needs to screen a large number of chips and make statistics on abnormal conditions. Because the testing tool on the hand is relatively crude, a batch of tests may require manually toggling the test switch tens of thousands of times, and convenience and accuracy are difficult to ensure. Due to the poor accuracy, the statistics result is not accurate enough, many detail problems may be ignored, and the reasons for the abnormality are more difficult to be examined. Therefore, how to solve the problems of low testing efficiency and difficult guarantee of accuracy of the chip is a technical problem to be solved urgently by those skilled in the art. Disclosure of Invention Therefore, the present invention aims to provide a method, a system, a device and a storage medium for testing chips, which can simplify the testing steps, improve the accuracy of the testing results and the statistical results, and improve the testing efficiency and quality. The specific scheme is as follows: A method of chip testing, comprising: The method comprises the steps of controlling the on or off of a relay to regulate and control the power-on time and the power-off time of a chip for a plurality of times, wherein the relay is electrically connected with a toggle switch of a chip test board, and the toggle switch is in a normally open state in the test process; Reading a test log of each power-on of the chip in real time; And acquiring the chip state in the test process according to the result read by the test log to judge whether to continue the test, and if not, acquiring the chip state in the test process to generate a statistical test result of the chip. Preferably, in the above chip testing method provided by the embodiment of the present invention, controlling the on or off of the relay includes: sending an opening instruction to a relay to control the opening of the relay; after waiting for the opening time corresponding to the opening instruction, sending an opening instruction to the relay, controlling the opening of the relay, and waiting according to the set time after opening; And circularly executing the operation of sending the opening instruction and the closing instruction to the relay. Preferably, in the above chip testing method provided by the embodiment of the present invention, before controlling the on or off of the relay, the method further includes: Setting the parameters to be counted to zero, opening the log file and the statistic file, and outputting a log file handle and a statistic file handle, wherein the parameters to be counted comprise the number of measured slices, the number of passing, the first abnormal constant, the probability abnormal constant and the probability abnormal time statistic array. Preferably, in the above method for testing a chip provided by the embodiment of the present invention, obtaining, according to the test log, a chip state in a test process to determine whether to continue the test, including: judging whether the test log contains a section passing the test or a section with abnormal test, and obtaining a judgment result of the read log; judging whether the cycle times are greater than the set times or not to obtain a judging result of the cycle times; and acquiring the state of the chip in the test process according to the judgment result of the reading log and the cycle times so as to judge whether to continue the test. Preferably, in the above chip testing method provided by the embodiment of the present invention, when acquiring a chip state in a testing process, the method further includes: Selecting to light a continuous test indicator lamp, an abnormal sign indicator lamp or a system fault indicator lamp; If the abnormal sign indicator lamp is lightened, judging whether the chip is abnormal in power-on for the first time, if so, updating the first abnormal constant, if not, updating th