CN-116577632-B - Method, device, equipment and medium for detecting critical path in integrated circuit

Abstract

The application provides a method, a device, equipment and a medium for detecting a critical path in an integrated circuit, and relates to the technical field of chips. The method comprises the steps of obtaining a gate-level netlist of a target integrated circuit, obtaining candidate critical paths with logic levels meeting preset requirements in the target integrated circuit based on the gate-level netlist, wherein the candidate critical paths comprise at least one target logic component, obtaining target logic relations of all the target logic components in the candidate critical paths, and determining that the candidate critical paths to which the target logic components belong are the target critical paths if the target logic relations meet the preset logic requirements, so that the candidate critical paths can be determined according to the logic levels of all initial paths in the target integrated circuit, and further screening the target critical paths based on the target logic relations of all the target logic components in the candidate critical paths.

Inventors

• WANG CUINA

Assignees

• 飞腾信息技术有限公司

Dates

Publication Date

20260505

Application Date

20230317

Claims (7)

1. 1. A method for detecting critical paths in an integrated circuit, comprising: Obtaining a gate-level netlist of a target integrated circuit, and obtaining a candidate critical path of which the logic level number meets preset requirements in the target integrated circuit based on the gate-level netlist, wherein the candidate critical path comprises at least one target logic component; acquiring a target logic relationship of each target logic component in the candidate critical path; If the target logic relationship is determined to meet the preset logic requirement, determining that the candidate critical path to which the target logic component belongs is a target critical path; the obtaining the candidate critical path of the logic level number meeting the preset requirement in the target integrated circuit based on the gate level netlist comprises the following steps: Traversing each initial path in the path set, determining a logic level number corresponding to each initial path, and determining a candidate critical path of which the logic level number meets preset requirements in the target integrated circuit according to the logic level number corresponding to each initial path; Traversing each initial path in the path set, and determining a logic level number corresponding to each initial path, wherein the logic level number comprises: Traversing each initial path in the path set to obtain the type of the logic component in each initial path; according to the types of logic components in the initial paths, eliminating preset logic components in the initial paths to obtain eliminated initial paths, wherein the preset logic components comprise an inverter and a buffer unit; Or alternatively, the first and second heat exchangers may be, And taking each initial path as a variable to be transmitted into a preset script, traversing each initial path in the path set through the preset script, and determining the logic series corresponding to each initial path.
2. 2. The method according to claim 1, wherein if the target logical relationship is determined to meet a preset logical requirement, determining the candidate critical path to which the target logical component belongs as the target critical path includes: If the target logic relationship indicates that the candidate critical path to which the target logic component belongs comprises at least two target logic components, and the output of a first target logic component in the at least two target logic components is the input of a second target logic component, and the output of the second target logic component is the input of the first target logic component, determining that the candidate critical path to which the target logic component belongs is the target critical path; Or alternatively, the first and second heat exchangers may be, And if the target logic relationship indicates that the output of any third target logic component is used as the input of the third target logic component, determining that the candidate critical path to which the target logic component belongs is a target critical path.
3. 3. The method according to claim 1, wherein the method further comprises: outputting path information corresponding to the target critical path based on the target critical path, wherein the path information comprises at least one of identification of each target logic component in the target critical path, target logic level corresponding to the target critical path and target logic relation corresponding to the target critical path; And adjusting the target critical path according to the path information corresponding to the target critical path so as to enable the output frequency of the target critical path to meet the preset frequency requirement.
4. 4. A method according to any one of claims 1-3, wherein the target logic comprises registers and/or static random access memory.
5. 5. A device for detecting critical paths in an integrated circuit, comprising: The first acquisition module is used for acquiring a gate-level netlist of a target integrated circuit, and acquiring a candidate critical path of which the logic level in the target integrated circuit meets the preset requirement based on the gate-level netlist, wherein the candidate critical path comprises at least one target logic component; The second acquisition module is used for acquiring the target logic relationship of each target logic component in the candidate critical path; the determining module is used for determining that the candidate critical path to which the target logic component belongs is a target critical path if the target logic relationship is determined to meet the preset logic requirement; The first obtaining module is specifically configured to obtain a path set of the target integrated circuit based on the gate-level netlist, where the path set includes at least one initial path; traversing each initial path in the path set, and determining a logic level corresponding to each initial path; according to the logic level number corresponding to each initial path, determining candidate critical paths with the logic level number meeting preset requirements in the target integrated circuit; Traversing each initial path in the path set, and determining a logic level number corresponding to each initial path, wherein the logic level number comprises: Traversing each initial path in the path set to obtain the type of the logic component in each initial path; according to the types of logic components in the initial paths, eliminating preset logic components in the initial paths to obtain eliminated initial paths, wherein the preset logic components comprise an inverter and a buffer unit; Or alternatively, the first and second heat exchangers may be, And taking each initial path as a variable to be transmitted into a preset script, traversing each initial path in the path set through the preset script, and determining the logic series corresponding to each initial path.
6. 6. An electronic device comprising a processor, a storage medium and a bus, the storage medium storing machine-readable instructions executable by the processor, the processor and the storage medium communicating over the bus when the electronic device is in operation, the processor executing the machine-readable instructions to perform the steps of the method of critical path detection in an integrated circuit as claimed in any of claims 1-4.
7. 7. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, performs the steps of the method for detecting critical paths in an integrated circuit according to any of claims 1-4.

Description

Method, device, equipment and medium for detecting critical path in integrated circuit Technical Field The present application relates to the field of chip technologies, and in particular, to a method, an apparatus, a device, and a medium for detecting a critical path in an integrated circuit. Background Along with the increasing of chip integration level and the decreasing of process size, the pursuit of frequency is also higher, and how to quickly locate the critical path in the design, timely feed back to the front-end engineer for modification becomes an essential ring in the frequency improvement work. In the prior art, when a critical path in an integrated circuit is located, a static timing analysis tool is often required to perform continuous analysis on a synthesized netlist of the integrated circuit, and the synthesized netlist is determined through continuous iterative design. It can be seen that the existing critical path detection method is complex, and has the problem of low detection efficiency. Disclosure of Invention The application aims to provide a method, a device, equipment and a medium for detecting a critical path in an integrated circuit, aiming at the defects in the prior art, and the method can improve the positioning efficiency of a target critical path in a target integrated circuit. In order to achieve the above purpose, the technical scheme adopted by the embodiment of the application is as follows: In a first aspect, the present invention provides a method for detecting a critical path in an integrated circuit, including: Obtaining a gate-level netlist of a target integrated circuit, and obtaining a candidate critical path of which the logic level number meets preset requirements in the target integrated circuit based on the gate-level netlist, wherein the candidate critical path comprises at least one target logic component; acquiring a target logic relationship of each target logic component in the candidate critical path; and if the target logic relationship meets the preset logic requirement, determining that the candidate critical path to which the target logic component belongs is the target critical path. In an optional implementation manner, if it is determined that the target logic relationship meets a preset logic requirement, determining that the candidate critical path to which the target logic component belongs is the target critical path includes: And if the target logic relationship indicates that the candidate critical path to which the target logic component belongs comprises at least two target logic components, and the output of a first target logic component in the at least two target logic components is the input of a second target logic component, and the output of the second target logic component is the input of the first target logic component, determining that the candidate critical path to which the target logic component belongs is the target critical path, or if the target logic relationship indicates that the output of any third target logic component is the input of the third target logic component, determining that the candidate critical path to which the target logic component belongs is the target critical path. In an alternative embodiment, the method further comprises: outputting path information corresponding to the target critical path based on the target critical path, wherein the path information comprises at least one of identification of each target logic component in the target critical path, target logic level corresponding to the target critical path and target logic relation corresponding to the target critical path; And adjusting the target critical path according to the path information corresponding to the target critical path so as to enable the output frequency of the target critical path to meet the preset frequency requirement. In an optional implementation manner, the obtaining, based on the gate-level netlist, a candidate critical path with a logic level meeting a preset requirement in the target integrated circuit includes: acquiring a path set of the target integrated circuit based on the gate-level netlist, wherein the path set comprises at least one initial path; Traversing each initial path in the path set, and determining a logic level corresponding to each initial path; And determining candidate critical paths with logic progression meeting preset requirements in the target integrated circuit according to the logic progression corresponding to each initial path. In an optional implementation manner, the traversing each initial path in the path set, determining a logic level corresponding to each initial path, includes: traversing each initial path in the path set to obtain the type of the logic component in each initial path; According to the types of logic components in the initial paths, eliminating preset logic components in the initial paths to obtain initial paths after elimination, wherein the preset logic com