CN-116610176-B - Voltage regulator including charge pump circuit

Abstract

The present disclosure relates to voltage regulators including charge pump circuits. In an embodiment, a voltage regulator has an input node that receives an input voltage and an output node. The voltage regulator has a charge pump circuit that receives a boost control signal to boost an input voltage based on the boost control signal. The voltage regulator also has a feedback regulation circuit configured to receive the output voltage and provide a first operational control signal and a second operational control signal in accordance with the output voltage, a stage control circuit configured to receive the first operational control signal and control the boost control signal in accordance with the first operational control signal, and a filter coupled to the output node and configured to receive the second operational control signal and configured to inject charge into or absorb charge from the output node in accordance with the second operational control signal.

Inventors

• L. Cam page
• M card Thimi
• M. Pasolini
• P. Romelle

Assignees

• 意法半导体股份有限公司

Dates

Publication Date

20260512

Application Date

20230214

Priority Date

20220215

Claims (20)

1. 1. A voltage regulator, comprising: a charge pump circuit coupled between an input node of the voltage regulator and an output node of the voltage regulator, the charge pump circuit configured to generate an output voltage at the output node based on a respective boost control signal, the output voltage having a boost value relative to an input voltage received at the input node; A feedback regulation circuit configured to generate a first operation control signal and a second operation control signal from the output voltage; A stage control circuit configured to generate a boost control signal according to the first operation control signal, and A filter configured to inject charge into or sink charge from the output node, the charge being based on the second operation control signal.
2. 2. The voltage regulator of claim 1, wherein the filter comprises a capacitive element having a first terminal and a second terminal, the first terminal coupled to the output node, and the second terminal configured to receive the second operation control signal.
3. 3. The voltage regulator of claim 1, wherein the feedback regulation circuit comprises an inverter configured to receive the first operation control signal and generate the second operation control signal.
4. 4. The voltage regulator of claim 3, wherein the inverter is a first inverter, the feedback regulation circuit further comprising a second inverter configured to receive the second operation control signal and generate a third operation control signal, the filter comprising a capacitive element having a first terminal and a second terminal, the first terminal coupled to the output node, and the second terminal configured to receive the third operation control signal.
5. 5. The voltage regulator of claim 4, wherein the first inverter has a first response time when generating the second operation control signal in response to a switch of the first operation control signal, and wherein the second inverter has a second response time when generating the third operation control signal in response to a switch of the second operation control signal, the second response time being greater than the first response time.
6. 6. The voltage regulator of claim 1, wherein the feedback regulation circuit comprises a comparator configured to: Comparing the output voltage with a reference voltage; switching the first operation control signal to a first value in response to the output voltage being greater than the reference voltage, and The first operation control signal is switched to a second value in response to the output voltage being less than the reference voltage.
7. 7. The voltage regulator of claim 6, wherein the phase control circuit is configured to: Disabling boosting of the input voltage by the charge pump circuit in response to the first operation control signal switching to the first value, and Boosting of the input voltage by the charge pump circuit is enabled in response to the first operation control signal switching to the second value.
8. 8. The voltage regulator according to claim 1, wherein the voltage regulator is a voltage regulator of a nonvolatile memory.
9. 9. The voltage regulator of claim 8, wherein the non-volatile memory is a phase change memory.
10. 10.A method for operating a voltage regulator, comprising: generating, by a charge pump circuit of the voltage regulator, an output voltage at an output node of the voltage regulator, the output voltage being a boost value relative to an input voltage received at an input node of the voltage regulator, the output voltage being based on a respective boost control signal, the charge pump circuit being coupled between the input node and the output node; Generating, by a feedback regulation circuit of the voltage regulator, a first operation control signal and a second operation control signal from the output voltage; Generating a boost control signal from the first operation control signal by a stage control circuit of the voltage regulator, and Charge is injected into or absorbed from the output node by a filter of the voltage regulator, the charge being based on the second operation control signal.
11. 11. The method of claim 10, wherein generating the second operation control signal comprises inverting the first operation control signal to generate the second operation control signal.
12. 12. The method of claim 10, wherein the filter comprises a first capacitive element having a first terminal coupled to the output node, the method further comprising receiving the second operation control signal at a second terminal of the first capacitive element.
13. 13. The method of claim 12, wherein the filter comprises a second capacitive element having a first terminal coupled to the output node, the method further comprising: generating a third operation control signal by the feedback regulation circuit, and The third operation control signal is received by a second terminal of the second capacitive element, the third operation control signal being an inverted signal relative to the second operation control signal.
14. 14. The method of claim 10, further comprising: Comparing the output voltage with a reference voltage; switching the first operation control signal to a first value in response to the output voltage being greater than the reference voltage, and The first operation control signal is switched to a second value in response to the output voltage being less than the reference voltage.
15. 15. The method of claim 10, wherein the step of injecting into or sinking from the output node is performed faster than the step of providing the respective boost control signal to the charge pump circuit by the phase control circuit.
16. 16. An apparatus comprising a non-volatile memory having a voltage regulator, the voltage regulator comprising: A charge pump circuit coupled between an input node of the voltage regulator and an output node of the voltage regulator, the charge pump circuit configured to generate an output voltage at the output node based on a respective boost control signal, the output voltage having a boost value relative to an input voltage received at the input node; A feedback regulation circuit configured to generate a first operation control signal and a second operation control signal from the output voltage; A stage control circuit configured to generate a boost control signal according to the first operation control signal, and A filter configured to inject charge into or sink charge from the output node, the charge being based on the second operation control signal.
17. 17. The apparatus of claim 16, wherein the filter comprises a capacitive element having a first terminal and a second terminal, the first terminal coupled to the output node and the second terminal configured to receive the second operation control signal, and wherein the feedback adjustment circuit comprises an inverter configured to receive the first operation control signal and to generate the second operation control signal.
18. 18. The apparatus of claim 17, wherein the inverter is a first inverter, the feedback conditioning circuit further comprises a second inverter configured to receive the second operational control signal and generate a third operational control signal, the filter comprises a capacitive element having a first terminal and a second terminal, the first terminal coupled to the output node, and the second terminal configured to receive the third operational control signal.
19. 19. The apparatus of claim 18, wherein the first inverter has a first response time when generating the second operation control signal in response to switching of the first operation control signal, and wherein the second inverter has a second response time when generating the third operation control signal in response to switching of the second operation control signal, the second response time being greater than the first response time.
20. 20. The apparatus of claim 16, wherein the feedback adjustment circuit comprises a comparator configured to: Comparing the output voltage with a reference voltage; switching the first operation control signal to a first value in response to the output voltage being greater than the reference voltage, and Switching the first operation control signal to a second value in response to the output voltage being less than the reference voltage, and Wherein the phase control circuit is configured to: Disabling boosting of the input voltage by the charge pump circuit in response to the first operation control signal switching to the first value, and Boosting of the input voltage by the charge pump circuit is enabled in response to the first operation control signal switching to the second value.

Description

Voltage regulator including charge pump circuit Cross Reference to Related Applications The present application claims priority from italian application No.102022000002786 filed on month 2 and 15 of 2022, which application is incorporated herein by reference in its entirety. Technical Field The present invention relates generally to voltage regulators and, in particular embodiments, to a voltage regulator having a charge pump circuit. Background In general, a voltage regulator having a charge pump circuit is used to generate an output voltage higher than a corresponding input voltage (i.e., operates as a DC-DC boost converter) by controlling charge transfer with a clock between capacitors serving as charge accumulating elements. In particular, in SoC (system on a chip) applications, it is often necessary to generate high internal voltages to drive specific circuit blocks. For example, charge pump circuits are used in non-volatile memories, such as flash, EEPROM or PCM types, in which programming and erasing operations are performed by applying voltages to the memory cells that are higher than the internal supply voltages available within the memory. Fig. 1 shows a block diagram of a known voltage regulator 1 comprising a charge pump circuit 5 coupled between an input node 6 at an input voltage V IN and an output node 7 at an output voltage V OUT. A capacitive load 9 having a capacitance C L is coupled between the output node 7 and ground. The charge pump circuit 5 comprises one or more charge pump stages, e.g. voltage multipliers, not shown here, cascaded (or connected in series) between an input node 6 and an output node 7. The voltage regulator 1 provides on-off regulation of the charge pump circuit 5 (i.e., it has a control loop circuit configured to control activation of the charge pump circuit 5) such that the output voltage V OUT remains at the reference required voltage V REF. The voltage regulator 1 comprises a comparator 11 receiving an output voltage V OUT and a reference voltage V REF and providing a STOP signal STOP, an oscillator 13 coupled to the output of the comparator 11 and providing a clock signal CLK, and a logic circuit 15 receiving the clock signal CLK and an input voltage V IN and providing a phase or boost signal PHASES to the charge pump circuit 5. The phase signal PHASES is a square wave signal having the frequency of the clock signal CLK and controlling the function of the stage of the charge pump circuit 5. As shown in the timing diagram of fig. 2, in use, the voltage regulator 1 has an on phase in which the output voltage V OUT is less than the reference voltage V REF and an off phase in which the output voltage V OUT is greater than the reference voltage V REF. In the on-phase, the comparator 11 keeps the STOP signal STOP at a low value, and the logic circuit 15 switches the phase signal PHASES between a low value and a high value to activate the charge pump circuit 5 and increase the value of the output voltage V OUT. In the off phase, the comparator 11 holds the STOP signal STOP at a high value and the logic circuit 15 freezes the commutation of the phase signal PHASES, thereby stopping the operation of the charge pump circuit 5. However, the voltage regulator 1, the comparator 11, the oscillator 13 and the logic circuit 15 each have a response time that introduces a delay at the active instants at which the active instants phases switch between. As shown in fig. 2, due to the delay of the comparator 11, the comparator 11 switches the STOP signal STOP to the high value at time t 2, effectively passing the reference voltage V REF with respect to the output voltage V OUT to delay the switching with respect to time t 1. Further, the timing t 3 at which the logic circuit 15 freezes the switching of the phase signal PHASES is delayed with respect to the timing t 2 due to the delay of the logic circuit 15. In practice, the output voltage V OUT remains increased above the reference voltage V REF between the time t 1 when the charge pump circuit 5 should cease to operate and the time t 2 when the charge pump circuit 5 ceases to operate. During the off phase, the output voltage V OUT decreases due to a discharge current flowing through a load 9 and other circuits (not shown here) connected at the output node 7 of the voltage regulator 1. After the output voltage V OUT drops below the reference voltage (time t 4), the comparator 11 switches the STOP signal STOP to a low value (time t 5) and the logic circuit 15 starts the commutation of the phase signal (time t 6). However, similarly to the above discussion, between the time t4 at which the charge pump circuit 5 should start operating and the time t6 at which the charge pump circuit 5 starts operating, the output voltage continues to decrease below the reference voltage V REF. In fact, in use, in voltage regulator 1, output voltage V OUT oscillates around reference voltage V REF, forming a ripple with peak-to-peak amplitude V R, for ex