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CN-116643159-B - Key detection circuit and key detection method

CN116643159BCN 116643159 BCN116643159 BCN 116643159BCN-116643159-B

Abstract

The invention provides a key detection circuit and a key detection method, wherein the circuit comprises a first key detection module, the first key detection module comprises m upper and lower pull branches and 1 lower pull branch, the m upper and lower pull branches are connected in parallel, each upper and lower pull branch is provided with an input and output interface, the input and output interfaces are connected with a pull-down key in the lower pull branch through a first diode in series, the second key detection module comprises N key detection units, the key detection units are connected with q input and output interfaces in the first key detection module in a one-to-one correspondence manner through q input and output terminals, and the connection modes of the key detection units and the first key detection module are different. Through above-mentioned button detection circuitry, can connect a plurality of buttons, a plurality of diode and a plurality of pull-up resistor through less input/output port to improve input/output port's availability factor, reduce processor input/output port's resource demand, reduce the complete machine cost.

Inventors

  • XUE JIA
  • PENG LONGFEI
  • ZHANG XUEDA
  • ZHONG CHUAN
  • LI ZONGHUA

Assignees

  • 深蓝汽车科技有限公司

Dates

Publication Date
20260505
Application Date
20230526

Claims (9)

  1. 1. A key detection circuit, the key detection circuit comprising: The first key detection module comprises m upward and downward pulling branches and 1 downward pulling branch, the m upward and downward pulling branches are connected in parallel, each upward and downward pulling branch comprises upward and downward pulling keys, each upward and downward pulling branch is provided with an input and output interface, in each upward and downward pulling branch, the upward and downward pulling keys are used for pulling up or down the input and output interface, the input and output interface is connected with the downward pulling keys in the downward pulling branch through a first diode in series, and the downward pulling keys are used for pulling down the input and output interface; the second key detection module comprises N key detection units, each key detection unit comprises N second diodes and N keys, each key detection unit is provided with q input and output terminals, the key detection units are in one-to-one correspondence connection with q input and output interfaces in the first key detection module through q input and output terminals, and the input and output terminals of each key detection unit are connected with the input and output interfaces which are combined in different sequences; The processor is configured to collect level signals of m input/output interfaces, or output fixed level signals to part of the input/output interfaces and collect level signals of the rest of the input/output interfaces, and then judge the opening and closing states of the pull-up key, the pull-down key and the keys according to the level signals of the m input/output interfaces, wherein, m, n, N, q is a positive integer, n takes a value of 5 and q takes a value of 3, each key detection unit is connected with 5 second diodes and 5 keys, the 5 second diodes comprise a first second diode, a second diode, a third second diode, a fourth second diode and a fifth second diode, the 5 keys comprise a first key, a second key, a third key, a fourth key and a fifth key, the 3 input/output terminals comprise a first input/output terminal, a second input/output terminal and a third input/output terminal, the 3 input/output terminal comprises a first input/output terminal, a second input/output terminal and a first input/output terminal, a first input/output terminal and a second terminal, and a third input/output terminal, and a first input/output terminal and a third input/output terminal are connected to the first terminal, and the second input/output terminal is connected to the first terminal and the first terminal, the second input/output terminal is connected to the first terminal and the first input/output terminal is connected to the first terminal through the first terminal, the first terminal and the first input/the first terminal is connected to the first terminal; The first input and output terminal is connected with one end of a second diode, the other end of the second diode is connected with one end of a second key, the other end of the second key is connected with one end of a first second diode, and the other end of the first second diode is connected with a third input and output terminal; one end of a third second diode is connected through the first input/output terminal, the other end of the third second diode is connected with one end of a third key, and the other end of the third key is connected with the second input/output terminal; One end of a fourth second diode is connected through a second input/output terminal, the other end of the fourth second diode is connected with one end of a second key, the other end of the second key is connected with one end of a first second diode, and the other end of the first second diode is connected with a third input/output terminal; The second input and output terminal is connected with one end of a fourth key, the other end of the fourth key is connected with one end of a first second diode, and the other end of the first second diode is connected with a third input and output terminal; The second input and output terminal is connected with one end of a fifth key, the other end of the fifth key is connected with one end of a fifth second diode, and the other end of the fifth second diode is connected with the first input and output terminal.
  2. 2. The key detection circuit according to claim 1, wherein each pull-up and pull-down branch comprises 1 pull-up resistor and 1 pull-up and pull-down key, one end of the pull-up resistor is connected to the power supply, the other end is connected to one end of the pull-up and pull-down key, and the other end of the pull-up key is grounded.
  3. 3. The key detection circuit according to claim 1, wherein the pull-down branch comprises a first diode and a pull-down key, one end of the first diode is connected to the input/output interface, the other end of the first diode is connected to one end of the pull-down key, and the other end of the pull-down key is grounded.
  4. 4. The key detection circuit of claim 1, wherein the key detection circuit is configured to detect the key by Calculating the maximum number of key detection units, the number of key detection units And each.
  5. 5. The key detection method is applied to the key detection circuit of any one of claims 1 to 4, and is characterized in that the key detection method comprises the steps that the m input/output interfaces are configured as first output interfaces, the processor collects level signals of the m input/output interfaces, and the opening and closing states of the pull-up key and the pull-down key are judged according to the level signals of the m first output interfaces; the m input/output interfaces are configured as second output interfaces, the other part is configured as an input interface, the processor outputs the fixed level signal to the input interface, the processor collects the level signal of the second output interface, and the opening and closing states of the keys are judged according to the level signal of the second output interface and the level signal of the input interface.
  6. 6. The key detection method according to claim 5, wherein m has a value of 3, the m input/output interfaces are partially configured as a second output interface, the other part is configured as an input interface, the processor outputs the fixed level signal to the input interface, the processor collects the level signal of the second output interface, and determines the open/close state of the key according to the level signal of the second output interface and the level signal of the input interface, including configuring the first input/output interface as the second output interface, the second input/output interface as the second output interface, the third input/output interface as the input interface, the output interface is configured as the key detection circuit outputting the level signal to the microprocessor, and the input interface is configured as the microprocessor inputting the level signal to the key detection circuit; if the input interface is a low-level signal, when the first input/output interface is detected to be low-level and the second input/output interface is detected to be high-level, the first key is judged to be closed; When the first input/output interface and the second input/output interface are detected to be low levels, the second key is judged to be closed; and when the first input/output interface is detected to be at a high level and the second input/output interface is detected to be at a low level, determining that the fourth key is closed.
  7. 7. The key detection method according to claim 6, wherein m has a value of 3, the m input/output interfaces are partially configured as a second output interface, the other part is configured as an input interface, the processor outputs the fixed level signal to the input interface, the processor collects the level signal of the second output interface, and determines the open/close state of the key according to the level signal of the second output interface and the level signal of the input interface, and further comprises configuring the second input/output interface as an input interface, the first input/output interface as a second output interface, and the third input/output interface as a high-impedance state; if the input interface is a low level signal, and the first input/output interface is detected to output a low level, the third key is judged to be closed.
  8. 8. The key detection method according to claim 6, wherein m has a value of 3, the m input/output interfaces are partially configured as a second output interface, the other part is configured as an input interface, the processor outputs the fixed level signal to the input interface, the processor collects the level signal of the second output interface, and determines the open/close state of the key according to the level signal of the second output interface and the level signal of the input interface, and further comprising configuring the first input/output interface as an input interface, the second input/output interface as a second output interface, and the third input/output interface as a high-impedance state; If the input interface is a low level signal, and the second input/output interface is detected to output a low level, the fifth key is judged to be closed.
  9. 9. The key detection method according to claim 6, wherein the m values are 3, the m input/output interfaces are configured as first output interfaces, the processor collects level signals of the m first output interfaces, and determines the open/close states of the pull-up key and the pull-down key according to the level signals of the m first output interfaces, including determining that the sixth key is closed if the first input/output interface is detected as low level, the second input/output interface is detected as high level, and the third input/output interface is detected as high level; If the first input/output interface is detected to be at a high level, the second input/output interface is detected to be at a low level, and the third input/output interface is detected to be at a high level, the seventh key is judged to be closed; if the first input/output interface is detected to be high level, the second input/output interface is detected to be high level, and the third input/output interface is detected to be low level, the eighth key is judged to be closed; If the first input/output interface is detected to be at a low level, the second input/output interface is detected to be at a low level, and the third input/output interface is detected to be at a low level, the ninth key is judged to be closed; If the first input/output interface is detected to be at the high level, the second input/output interface is detected to be at the high level, and the third input/output interface is detected to be at the high level, all keys are judged to be disconnected.

Description

Key detection circuit and key detection method Technical Field The invention relates to the technical field of electronics, in particular to a key detection circuit and a key detection method. Background The key detection circuit is quite widely applied to electronic products, one key is directly connected with one Input/Output port (i.e. one-to-one connection mode) of a controller, but the key detection circuit is simple and direct, and because one key needs to monopolize one Input/Output port of the controller, when more keys are needed, more I/O ports (how many keys are needed and how many I/O ports are needed) of the controller are needed, so that the utilization rate of the I/O ports of the controller is low. The invention patent application number 201110458536.4 discloses a non-AD port key detection circuit, according to the circuit structure provided by the invention, 6 keys can be detected by using 2I/O ports which are not AD (analog to digital), and on the basis, the detection of 12 keys by 4I/O ports can be realized. But this circuit configuration does not enable detection if a greater number of keys are detected using the same number of non-AD I/O ports. Disclosure of Invention The invention provides a key detection circuit and a key detection method, which are used for solving the technical problem that the opening and closing states of keys can not be detected due to more keys. The embodiment of the invention provides a key detection circuit, which comprises: the first key-press detection module is used for detecting the first key-press, the first key detection module comprises m upper and lower pull branches and 1 lower pull branch, the m upper and lower pull branches are connected in parallel, each upper and lower pull branch comprises an upper and lower pull key, each upper and lower pull branch is provided with an input and output interface, in each of the pull-up and pull-down branches, the input/output interface is pulled up or pulled down through the pull-up and pull-down keys, the input/output interface is connected with a pull-down button in the pull-down branch through a first diode in series connection, the input/output interface is pulled down through the pull-down key; a second key detection module, which is used for detecting the second key, the second key detection module comprises N key detection units, each key detection unit comprises N second diodes and N keys, each key detection unit is provided with q input and output terminals, the key detection unit is connected with q input/output interfaces in the first key detection module in a one-to-one correspondence manner through q input/output terminals, the connection modes of the key detection units and the first key detection modules are different; wherein, the m of the input-output interfaces are connected to a processor configured to: collecting level signals of m input/output interfaces, or outputting fixed level signals to part of the input/output interfaces, collecting level signals of the rest of the input/output interfaces, and judging the opening and closing states of the pull-up button, the pull-down button and the buttons according to the level signals of m input/output interfaces; wherein m, n, N, q are positive integers. In an embodiment of the present invention, each of the pull-up and pull-down branches includes 1 pull-up resistor and 1 pull-up button, one end of the pull-up resistor is connected to the power supply, the other end is connected to one end of the pull-up button, and the other end of the pull-up button is grounded. In an embodiment of the invention, the pull-down branch includes a first diode and a pull-down button, one end of the first diode is connected to the input/output interface, the other end of the first diode is connected to one end of the pull-down button, and the other end of the pull-down button is grounded. In one embodiment of the present invention, n has a value of 5 and q has a value of 3, each key detection unit is connected with 5 second diodes and 5 keys, the 5 second diodes include a first second diode, a second diode, a third second diode, a fourth second diode and a fifth second diode, the 5 keys comprise a first key, a second key, a third key, a fourth key and a fifth key, the 3 input-output terminals include a first input-output terminal, a second input-output terminal, and a third input-output terminal, including: in the 1-mentioned key detection unit, the first input/output terminal is connected with one end of a first key, the other end of the first key is connected with one end of a first second diode, and the other end of the first second diode is connected with a third input/output terminal; the first input and output terminal is connected with one end of a second diode, the other end of the second diode is connected with one end of a second key, the other end of the second key is connected with one end of a first second diode, and the other end of the first second dio