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CN-116645923-B - Display substrate, driving method thereof and display device

CN116645923BCN 116645923 BCN116645923 BCN 116645923BCN-116645923-B

Abstract

The display substrate comprises a display area and a peripheral area positioned at the periphery of the display area, wherein a plurality of pixel units and a plurality of light-emitting control signal lines are arranged in the display area, a first grid driving circuit and at least two first starting control signal lines are arranged in the peripheral area, the first grid driving circuit comprises at least two first shift register groups which are in one-to-one correspondence with the first starting control signal lines and are independent of each other, each first shift register group comprises at least two first shift registers which are cascaded, the signal output end of each first shift register is connected with the corresponding light-emitting control signal line, the signal input end of the first shift register positioned at a first stage is connected with the first starting control signal line configured by the first shift register group in the first shift register group, and the signal input end of any one first shift register except the first stage is connected with the signal output end of the first shift register positioned at the previous stage.

Inventors

  • FENG XUEHUAN
  • LI YONGQIAN

Assignees

  • 合肥京东方卓印科技有限公司
  • 京东方科技集团股份有限公司

Dates

Publication Date
20260512
Application Date
20220215

Claims (11)

  1. 1. The driving method of the display substrate is characterized in that the display substrate comprises a display area and a peripheral area positioned at the periphery of the display area, wherein a plurality of pixel units which are arranged in an array are arranged in the display area, and each row of pixel units is provided with a corresponding light-emitting control signal line; the peripheral area is internally provided with a first grid driving circuit and at least two first start control signal lines configured for the first grid driving circuit, the first grid driving circuit comprises at least two first shift register groups which are in one-to-one correspondence with the first start control signal lines and are independent of each other, the first shift register groups comprise at least two first shift registers which are cascaded, the first shift registers are provided with signal input ends and signal output ends, and the signal output ends of the first shift registers are connected with the corresponding light-emitting control signal lines; In the first shift register group, the signal input end of the first shift register positioned at a first stage is connected with the first start control signal line configured by the first shift register group, and the signal input end of any one of the first shift registers except the first stage is connected with the signal output end of the first shift register positioned at the previous stage; the first grid driving circuit comprises n first shift register groups, n is greater than 2, one frame comprises n-1 black inserting driving stages, and the first grid driving circuit is configured to sequentially provide an ith black inserting driving signal for each light-emitting control signal line in the ith black inserting driving stage, wherein i is greater than or equal to 1 and less than or equal to n-1; each black insertion driving stage is divided into a first sub-stage and a second sub-stage by a preset blank period, wherein the first sub-stage is positioned before the blank period, and the second sub-stage is positioned after the blank period; the driving method includes: In a first sub-stage in the ith black insertion driving stage, sequentially and respectively providing the ith black insertion driving start signals to first start control signal lines configured by the 1 st to n-i th first shift register groups, so that the first shift registers in the 1 st to n-i th first shift register groups sequentially output the ith black insertion driving signals; in the blank period, each first shift register does not output a black insertion driving signal; In a second sub-stage in the ith black insertion driving stage, the ith black insertion driving start signals are sequentially and respectively supplied to the first start control signal lines configured by the (n-i+1) -th to nth first shift register groups, so that the first shift registers in the (n-i+1) -th to nth first shift register groups sequentially output the ith black insertion driving signals.
  2. 2. The driving method of a display substrate according to claim 1, wherein the number of the first start control signal lines is 2 to 5.
  3. 3. The driving method of a display substrate according to claim 1, wherein the first shift register comprises: A first input circuit connected to a signal input terminal, a first clock signal terminal, and a second node, and configured to write a signal provided by the signal input terminal to the second node in response to control of a signal provided by the first clock signal terminal; The second input circuit is connected with a first clock signal end, a first power end and a second node and is configured to write a first working voltage provided by the first power end into a third node in response to control of signals provided by the first clock signal end and write signals provided by the first clock signal end into the third node in response to control of voltages at the second node; a first voltage control circuit connected to a second clock signal terminal, a second power supply terminal, a first node, a second node, and a third node, configured to write a signal provided by the second clock signal terminal to the first node in response to control of a voltage at the third node and a signal provided by the second clock signal terminal, and to write a second operating voltage provided by the second power supply terminal to the first node in response to control of a voltage at the second node; The second voltage control circuit is connected with a second clock signal end, a second power supply end and a third node and is configured to respond to the voltage at the third node and the signal provided by the second clock signal end to write the second working voltage provided by the second power supply end into the second node; And the output circuit is connected with the first power supply end, the second power supply end, the signal output end, the first node and the second node and is configured to write a second working voltage provided by the second power supply end into the signal output end in response to the control of the voltage at the first node and write a first working voltage provided by the first power supply end into the signal output end in response to the control of the voltage at the second node.
  4. 4. The method according to claim 3, wherein the first input circuit comprises a first transistor, wherein the second input circuit comprises a second transistor and a third transistor, wherein the first voltage control circuit comprises a fourth transistor, a fifth transistor, a sixth transistor, and a third capacitor, wherein the second voltage control circuit comprises a seventh transistor and an eighth transistor, and wherein the output circuit comprises a ninth transistor, a tenth transistor, a first capacitor, and a second capacitor; The control electrode of the first transistor is connected with a first clock signal end, the first electrode of the first transistor is connected with a signal input end, and the second electrode of the first transistor is connected with the second node; the control electrode of the second transistor is connected with the first clock signal end, the first electrode of the second transistor is connected with the second power supply end, and the second electrode of the second transistor is connected with the third node; A control electrode of the third transistor is electrically connected with the second node, a first electrode of the third transistor is connected with the third node, and a second electrode of the third transistor is connected with the first clock signal end; The control electrode of the fourth transistor is connected with the third node, the first electrode of the fourth transistor is connected with the second clock signal end, and the second electrode of the fourth transistor is connected with the fourth node; The control electrode of the fifth transistor is connected with the second clock signal end, the first electrode of the fifth transistor is connected with the fourth node, and the second electrode of the fifth transistor is connected with the first node; The control electrode of the sixth transistor is connected with the second node, the first electrode of the sixth transistor is connected with the first node, and the second electrode of the sixth transistor is connected with the second power supply end; the first end of the third capacitor is connected with the third node, and the second end of the third capacitor is connected with the fourth node; A control electrode of the seventh transistor is connected with the third node, a first electrode of the seventh transistor is connected with a second power supply end, and a second electrode of the seventh transistor is connected with a first electrode of the eighth transistor; the control electrode of the eighth transistor is connected with the second clock signal end, and the second electrode of the eighth transistor is connected with the second node; a control electrode of the ninth transistor is connected with the first node, a first electrode of the ninth transistor is connected with the second power supply end, and a second electrode of the ninth transistor is connected with the signal output end; The control electrode of the tenth transistor is connected with the second node, the first electrode of the tenth transistor is connected with the signal output end, and the second electrode of the tenth transistor is connected with the first power supply end; the first end of the first capacitor is connected with the first node, and the second end of the first capacitor is connected with the second power supply end; the first end of the second capacitor is connected with the signal output end, and the second end of the second capacitor is connected with the second node.
  5. 5. The method of driving a display substrate according to claim 3, wherein the first shift register further comprises a first anti-leakage circuit; The first input circuit, the second input circuit and the second node control voltage are connected to a fifth node, the first anti-leakage circuit is positioned between the fifth node and the second node, and the first input circuit, the second input circuit and the second voltage control circuit are all connected with the second node through the first anti-leakage circuit; the first anti-leakage circuit is further connected with the first power end and the third power end, and is configured to write a third working voltage provided by the third power end into a first anti-leakage node under the control of the voltage at the second node, and the first anti-leakage node is located between the second node and the fifth node.
  6. 6. The method of driving a display substrate according to claim 5, wherein the first leakage preventing circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor; the control electrode of the eleventh transistor is connected with the first power supply end, the first electrode of the eleventh transistor is connected with a fifth node, and the second electrode of the eleventh transistor is connected with the first anti-leakage node; the control electrode of the twelfth transistor is connected with the first power supply end, the first electrode of the twelfth transistor is connected with the first anti-leakage node, and the second electrode of the twelfth transistor is connected with the second node; the control electrode of the thirteenth transistor is connected with the second node, the first electrode of the thirteenth transistor is connected with the third power supply end, and the second electrode of the thirteenth transistor is connected with the first anti-leakage node.
  7. 7. The method according to claim 3, wherein the first shift register further comprises a second anti-leakage circuit, the output circuit is connected to a second power supply terminal through the second anti-leakage circuit, and the output circuit and the second anti-leakage circuit are connected to a second anti-leakage node; The second anti-leakage circuit is further connected with the first node, the first power end, the second power end and the signal output end, and is configured to write the first working voltage provided by the first power end into the second anti-leakage node in response to control of the voltage at the signal output end.
  8. 8. The method of driving a display substrate according to claim 7, wherein the second leakage preventing circuit includes a fourteenth transistor and a fifteenth transistor; a control electrode of the fourteenth transistor is connected with the first node, a first electrode of the fourteenth transistor is connected with the second power supply end, and a second electrode of the fourteenth transistor is connected with the second anti-leakage node; The control electrode of the fifteenth transistor is connected with the signal output end, the first electrode of the fifteenth transistor is connected with the first power supply end, and the second electrode of the fifteenth transistor is connected with the second anti-leakage node.
  9. 9. The driving method of a display substrate according to claim 8, wherein the first shift register further comprises: And the global reset circuit is connected with the global reset signal end, the first power end and the second node and is configured to respond to the control of signals provided by the global reset signal end to write the first working voltage provided by the first power end into the second node.
  10. 10. The method of driving a display substrate according to claim 9, wherein the global reset circuit includes a sixteenth transistor; The control electrode of the sixteenth transistor is connected with the global reset signal end, the first electrode of the sixteenth transistor is connected with the second node, and the second electrode of the sixteenth transistor is connected with the first power end.
  11. 11. The method according to any one of claims 3 to 10, wherein the first gate driving circuit is further configured with a first clock signal supply line and a second clock signal supply line arranged in a first direction, the first clock signal supply line and the second clock signal supply line each extending in a second direction; the first shift registers in the first gate driving circuit are sequentially arranged along the second direction, wherein a first clock signal end configured by a first shift register in an odd number of bits is connected with the first clock signal supply line, a second clock signal end configured by a first shift register in an odd number of bits is connected with the second clock signal supply line, a first clock signal end configured by a first shift register in an even number of bits is connected with the second clock signal supply line, and a second clock signal end configured by a first shift register in an even number of bits is connected with the first clock signal supply line.

Description

Display substrate, driving method thereof and display device Technical Field The present invention relates to the field of display, and in particular, to a display substrate, a driving method thereof, and a display device. Background Active matrix organic light emitting Diode panels (Active Matrix Organic LIGHT EMITTING Diode, AMOLED for short) are becoming increasingly popular. The pixel display device of the AMOLED is an Organic Light-Emitting Diode (OLED), and the AMOLED is capable of Emitting Light by driving a thin film transistor to generate a driving current in a saturated state, and the driving current drives the Light-Emitting device to emit Light. Disclosure of Invention In a first aspect, an embodiment of the present disclosure provides a display substrate, including a display area and a peripheral area located at the periphery of the display area, where a plurality of pixel units arranged in an array are disposed in the display area, and each row of pixel units is configured with a corresponding light emission control signal line; the peripheral area is internally provided with a first grid driving circuit and at least two first start control signal lines configured for the first grid driving circuit, the first grid driving circuit comprises at least two first shift register groups which are in one-to-one correspondence with the first start control signal lines and are independent of each other, the first shift register groups comprise at least two first shift registers which are cascaded, the first shift registers are provided with signal input ends and signal output ends, and the signal output ends of the first shift registers are connected with the corresponding light-emitting control signal lines; In the first shift register group, the signal input end of the first shift register located at a first stage is connected to the first start control signal line configured by the first shift register group, and the signal input end of any one of the first shift registers other than the first stage is connected to the signal output end of the first shift register of the preceding stage. In some embodiments, the number of first start control signal lines is 2 to 5. In some embodiments, the first shift register includes: A first input circuit connected to a signal input terminal, a first clock signal terminal, and a second node, and configured to write a signal provided by the signal input terminal to the second node in response to control of a signal provided by the first clock signal terminal; The second input circuit is connected with a first clock signal end, a first power end and a second node and is configured to write a first working voltage provided by the first power end into a third node in response to control of signals provided by the first clock signal end and write signals provided by the first clock signal end into the third node in response to control of voltages at the second node; a first voltage control circuit connected to a second clock signal terminal, a second power supply terminal, a first node, a second node, and a third node, configured to write a signal provided by the second clock signal terminal to the first node in response to control of a voltage at the third node and a signal provided by the second clock signal terminal, and to write a second operating voltage provided by the second power supply terminal to the first node in response to control of a voltage at the second node; The second voltage control circuit is connected with a second clock signal end, a second power supply end and a third node and is configured to respond to the voltage at the third node and the signal provided by the second clock signal end to write the second working voltage provided by the second power supply end into the second node; And the output circuit is connected with the first power supply end, the second power supply end, the signal output end, the first node and the second node and is configured to write a second working voltage provided by the second power supply end into the signal output end in response to the control of the voltage at the first node and write a first working voltage provided by the first power supply end into the signal output end in response to the control of the voltage at the second node. In some embodiments, the first input circuit includes a first transistor, the second input circuit includes a second transistor and a third transistor, the first voltage control circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a third capacitance, the second voltage control circuit includes a seventh transistor and an eighth transistor, and the output circuit includes a ninth transistor, a tenth transistor, a first capacitance, and a second capacitance; The control electrode of the first transistor is connected with a first clock signal end, the first electrode of the first transistor is connected with a signal input end, and the second electrode