CN-116699956-B - Method for designing holographic super surface by on-chip and free space multiplexing

CN116699956BCN 116699956 BCN116699956 BCN 116699956BCN-116699956-B

Abstract

The invention discloses a method for designing a holographic super-surface for on-chip and free space multiplexing, which comprises the steps of designing a super-surface structure, calculating resonance phase response distribution and transmittance distribution of a silicon nano-block in the super-surface under an on-chip input light source and a free space input light source, designing different holographic patterns, inputting the different holographic patterns into a GS algorithm to obtain the phase distribution of the super-surface corresponding to a holographic image, generating the phase distribution of 3 super-surfaces, determining the geometric dimension and the relative position of all the silicon nano-blocks on the super-surface according to the resonance phase response distribution and the transmittance distribution and the phase distribution of the super-surface obtained in the step 3), and determining the holographic super-surface structure for on-chip and free space multiplexing to finish the design. The invention can solve the problem of limited application of the on-chip super surface, and provides a new super surface holographic display multiplexing thought, and three-channel holographic multiplexing under the same wavelength can be realized by combining the detour phase and resonance phase principles.

Inventors

LI WENWEN
MA WEI
XIONG BO
CHU TAO

Assignees

浙江大学

Dates

Publication Date: 20260508
Application Date: 20230529

Claims (4)

1. A method of designing an on-chip and free-space multiplexed holographic super surface, comprising the steps of: 1) Designing a super-surface structure; 2) Calculating resonance phase response distribution and transmittance distribution of the silicon nano block in the super surface under the on-chip input light source and the free space input light source, wherein the method specifically comprises the following steps: Under the same working wavelength of an on-chip input light source and a free space input light source, calculating resonance phase response spectrums of silicon nano blocks with different geometric dimensions under the on-chip input light source, transmittance distribution transmitted in an optical waveguide layer in a super surface and resonance phase response spectrums and transmittance distribution under the free space input light source with different polarizations by a time domain finite difference method; 3) Designing different holographic patterns, inputting the different holographic patterns into a GS algorithm, obtaining the phase distribution of the super-surface corresponding to the holographic image, and generating the phase distribution of 3 super-surfaces; 4) Determining the geometric dimensions and the relative positions of all the silicon nano blocks on the super surface according to the resonance phase response distribution and the transmittance distribution obtained in the step 2) and the phase distribution of the super surface obtained in the step 3), and determining the structures of the holographic super surface multiplexed on the chip and the free space, so as to complete the design; determining the geometric dimensions and the relative positions of all the silicon nano-blocks on the super-surface according to the resonance phase response distribution and the transmittance distribution obtained in the step 2) and the phase distribution of the super-surface obtained in the step 3), wherein the method specifically comprises the following steps: 4.1 Firstly, using a resonance phase principle, corresponding 2 of the phase distributions of the 3 super-surfaces obtained in the step 3) to resonance phase response spectrums under the free space input light sources with different polarizations obtained in the step 2), ensuring that the corresponding transmittance of the finally obtained silicon nano-blocks is more than 80%, and determining the geometric dimensions of all the silicon nano-blocks on the super-surfaces; 4.2 The geometrical dimensions of all the silicon nano blocks on the super surface obtained in the step 4.1) correspond to the resonance phase response spectrums of the silicon nano blocks with different geometrical dimensions under the on-chip input light source obtained in the step 2), so that the super surface resonance phase distribution under the on-chip input light source is obtained; 4.3 Subtracting the rest 1 of the 3 super-surface phase distributions obtained in the step 3) from the super-surface resonance phase distribution under the on-chip input light source obtained in the step 4.2) to obtain the super-surface detour phase distribution under the on-chip input light source; 4.4 By using the detour phase principle, the relative positions of all the silicon nano-blocks on the super surface are obtained through calculation of the detour phase distribution of the super surface under the input light source on the chip obtained in the input step 4.3).
2. The method of claim 1, wherein in step 1), the super surface comprises a silica substrate, an optical waveguide layer disposed on the silica substrate, and a monoatomic amorphous silicon nano-block structure array disposed on the optical waveguide layer, the monoatomic amorphous silicon nano-block structure array comprising a plurality of silicon nano-blocks having the same height and arranged at different positions on the chip.
3. The method of designing an on-chip and free-space multiplexed holographic super surface of claim 2, wherein in step 1), said optical waveguide layer is a silicon nitride optical waveguide layer or a lithium niobate optical waveguide layer.
4. The method of designing holographic superpositions for on-chip and free space multiplexing as claimed in claim 1, wherein in step 2), the different polarizations are X linear polarization and Y linear polarization.

Description

Method for designing holographic super surface by on-chip and free space multiplexing Technical Field The invention relates to the technical field of optics, integrated photonics and optical communication information encryption, in particular to a method for designing a holographic super surface by on-chip and free space multiplexing. Background Most of the super-surfaces are driven by free-space light, and utilize the degrees of freedom of the wavelength, polarization, incident angle, etc. of the free-space light to realize the functions of beam deflection, focusing, hologram, etc., which makes it difficult to further integrate on a chip. The continuing trend toward miniaturized and versatile photonic systems simultaneously requires more complex device functions to be implemented in a more compact, multi-functional, configurable and CMOS compatible manner, which presents new challenges to traditional photonic integrated circuits. The nanometer manufacturing technology is improved continuously, and technical support is provided for the on-chip super surface. The combination of the super surface and the waveguide can inject new degrees of freedom into the photonic integrated device, and more complex functions are realized. At present, the existing on-chip super-surface research mainly utilizes the regulation and control mechanism of a detour phase (detourphase) to carry out on-chip holographic display, or combines the detour phase with a geometric phase (PB phase) to realize on-chip multiplexing, but the regulation and control mechanisms are relatively single, and the geometric phase determines that the super-surface can only work under circularly polarized light, so that the application of the on-chip super-surface is limited to a certain extent. Disclosure of Invention The invention provides a method for designing a holographic super-surface of on-chip and free space multiplexing, which is based on the method for displaying the holographic super-surface of the on-chip and free space, can solve the problem of limited application of the super-surface of the on-chip, and provides a novel super-surface holographic display multiplexing thought, and three-channel holographic multiplexing under the same wavelength can be realized by combining a detour phase and a resonance phase principle. The invention provides a design method of an on-chip and off-chip super-surface, which takes structural parameters of nano block unit structures forming the super-surface as a first phase influence factor, takes relative distances among nano block unit structures of the super-surface as a second phase influence factor, and combines the two phase influence factors to carry out arrangement design on the geometric structures and the relative positions of the nano block units of the super-surface, so that the super-surface can generate different target holograms at free space appointed positions under waveguide incident light and free space incident light. A method of designing an on-chip and free-space multiplexed holographic super surface, comprising the steps of: 1) Designing a super-surface structure; 2) Calculating resonance phase response distribution and transmittance distribution of the silicon nano block in the super surface under the on-chip input light source and the free space input light source; In the step 2), the resonance phase response distribution and the transmittance distribution of the silicon nano-block in the super surface under the on-chip input light source and the free space input light source are calculated, and the method specifically comprises the following steps: Under the same working wavelength of an on-chip input light source and a free space input light source, calculating resonance phase response spectrums of silicon nano blocks with different geometric dimensions under the on-chip input light source, transmittance distribution transmitted in an optical waveguide layer in a super surface and resonance phase response spectrums and transmittance distribution under the free space input light source with different polarizations by a time domain finite difference method; 3) Designing different holographic patterns, inputting the different holographic patterns into a GS (Gerchberg-Saxton) algorithm to obtain the phase distribution of the super-surface corresponding to the holographic image, and generating the phase distribution of 3 super-surfaces; 4) Determining the geometric dimensions and the relative positions of all the silicon nano blocks on the super surface according to the resonance phase response distribution and the transmittance distribution obtained in the step 2) and the phase distribution of the super surface obtained in the step 3); 5) And (3) determining the structure of the holographic super surface multiplexed on the chip and free space according to the geometric dimensions of all the silicon nano blocks on the super surface obtained in the step 4.1) and the relative positions of all