CN-116708872-B - Self-adaptive optimization circuit and equipment for video stream processing clock

Abstract

The invention relates to a self-adaptive optimization circuit and equipment for a video stream processing clock. The circuit comprises a video image receiver, a time sequence adjustment controller, an intra-row horizontal blanking area statistics module, an RC annular oscillation circuit controller, an RC annular oscillator, a fixed frequency clock, an intra-row total time monitoring module and a clock multiplexing switching circuit. The video stream processing clock signal frequency is reduced to one fourth of the pixel clock frequency through two line SRAM buffers, and then the RC annular oscillating circuit controller reduces the oscillating frequency of the RC annular oscillator according to the statistical result of the line horizontal blanking region statistical module until the output line horizontal blanking time is maintained to the minimum value required by the system. When the frame refresh rate increases, the clock multiplexing switching circuit immediately switches to a higher frequency signal, thereby achieving a balance of system performance and power consumption.

Inventors

• LI WENQI
• WANG XIN

Assignees

• 南京英科迪微电子科技有限公司

Dates

Publication Date

20260508

Application Date

20230628

Claims (6)

1. 1. The self-adaptive optimization circuit of the video stream processing clock is characterized by comprising a video image receiver, a time sequence adjustment controller, an intra-line horizontal blanking area statistics module, an RC annular oscillation circuit controller, an RC annular oscillator, a fixed frequency clock, an intra-line total time monitoring module and a clock multiplexing switching circuit; The output end of the video image receiver is respectively connected with the time sequence adjustment controller and the input end of the in-line total time monitoring module, the first output end of the time sequence adjustment controller is used for outputting video streams, the second output end of the time sequence adjustment controller is connected with the input end of the in-line horizontal blanking area statistics module, the output end of the in-line horizontal blanking area statistics module is connected with the input end of the RC ring oscillator circuit controller, the output end of the RC ring oscillator circuit controller is respectively connected with the input ends of the RC ring oscillator and the fixed frequency clock, the output ends of the RC ring oscillator, the fixed frequency clock and the in-line total time monitoring module are respectively connected with the input ends of the clock multiplexing switching circuit, and the output end of the clock multiplexing switching circuit is respectively connected with the input ends of the time sequence adjustment controller and the in-line horizontal blanking area statistics module; The video image receiver is used for receiving and analyzing an original video stream signal, outputting a timing control signal and a data channel signal, the line sequence adjustment controller is used for processing a clock signal according to the video stream generated by the timing control signal and the clock multiplexing switching circuit, alternately reading and writing the data channel signal through two SRAM buffers and outputting a video stream and a first data effective identifier, the line horizontal blanking area statistics module is used for counting the first data effective identifier according to the video stream processing clock signal, outputting a value of a line horizontal blanking area, the RC ring oscillation circuit controller is used for adjusting the oscillation frequency of the RC ring oscillator according to the value of the line horizontal blanking area, the RC ring oscillator is used for outputting a first clock signal according to the oscillation frequency, the fixed frequency clock is used for outputting a second clock signal, the line total time monitoring module is used for counting the effective pixel area identifier according to a recovered data clock, the clock multiplexing switching circuit is used for counting the first data effective identifier according to the video stream, outputting a value of the line horizontal blanking area according to the video stream processing clock signal, the RC ring oscillation frequency controller is used for increasing the oscillation frequency of the RC ring oscillator according to the oscillation frequency, the line total time monitoring module is used for increasing the frame rate of the video stream processing clock signal according to the recovered data clock signal, and the frame rate of the video stream processing clock signal is increased according to the recovered clock signal, and the frame rate of the video stream processing clock signal is increased by the first clock signal is increased, and the frame rate is increased by the clock rate is increased, and the frame rate is increased by the clock rate is increased by the frame rate; The RC ring-shaped oscillating circuit controller is internally integrated with a second register, the second register is used for storing a first configurable comparison threshold value and a minimum frequency threshold value, the first comparison threshold value is used for triggering the adjustment of the oscillating frequency, when the number of the horizontal blanking area in a row is smaller than the first comparison threshold value, the oscillating frequency of the RC ring-shaped oscillator is kept unchanged, when the number of the horizontal blanking area in the row is larger than the first comparison threshold value, the adjustable RC parameter of the RC ring-shaped oscillator is controlled to reduce the oscillating frequency, and the difference between the number of the horizontal blanking area in the row and the first comparison threshold value determines the amplitude to be adjusted of the output frequency, and the minimum frequency threshold value is the minimum protection value of the oscillating frequency.
2. 2. The adaptive optimization circuit of a video stream processing clock of claim 1, wherein the intra-row horizontal blanking interval statistics module is internally integrated with a first register, the first register is configured to store a configurable interval time parameter, and the interval time parameter is configured to determine a time range in which the intra-row horizontal blanking interval statistics module performs statistics on the first data valid identifier.
3. 3. The adaptive optimization circuit of the video stream processing clock of claim 1, wherein the intra-row total time monitor module has a third register integrated therein for storing a configurable second comparison threshold for triggering the setting of the intra-row total time reduction flag to a high level.
4. 4. A video stream processing clock adaptive optimization circuit as recited in any one of claims 1-3, wherein the fixed frequency clock is a clock phase locked loop.
5. 5. The adaptive optimization circuit of a video stream processing clock of claim 4 wherein the video image receiver receives and processes the raw video stream signal using an eDP or MIPI interface.
6. 6. A video stream processing device comprising an adaptive optimization circuit of a video stream processing clock according to any one of claims 1-5.

Description

Self-adaptive optimization circuit and equipment for video stream processing clock Technical Field The present invention relates to the field of image display and signal processing, and in particular, to an adaptive optimization circuit and apparatus for a video stream processing clock. Background The video stream is an object to be processed by the image receiving and processing system, and is composed of an image sequence, a certain processing resource is required to be consumed, and the change of the video stream can cause the change of the processing capacity of the system. The processing clock refers to a clock arranged in the image processing system, and the signal frequency of the processing clock controls the time sequence and the speed of the processing process of the system. In the chip, the image display and signal processing system needs to set a matched video stream processing clock according to the image resolution and the frame refresh rate, and is used for synchronizing and driving the system to acquire, process and output video stream data according to the set parameters. When image display and signal processing are performed, the high-frequency processing clock can increase the processing speed but increase the power consumption, and the low-frequency processing clock can reduce the power consumption but slow down the processing speed. The conventional video stream processing clock has the technical problem that the performance and the power consumption are difficult to balance. Disclosure of Invention Based on this, it is necessary to provide an adaptive optimization circuit of a video stream processing clock and a video stream processing apparatus. In order to achieve the above object, the embodiment of the present invention adopts the following technical scheme: in one aspect, an adaptive optimization circuit for a video stream processing clock is provided, including a video image receiver, a time sequence adjustment controller, an intra-line horizontal blanking region statistics module, an RC ring oscillator circuit controller, an RC ring oscillator, a fixed frequency clock, an intra-line total time monitoring module, and a clock multiplexing switching circuit. The output end of the video image receiver is respectively connected with the input ends of the time sequence adjustment controller and the in-line total time monitoring module, the first output end of the time sequence adjustment controller is used for outputting video streams, the second output end of the time sequence adjustment controller is connected with the input end of the in-line horizontal blanking region statistics module, the output end of the in-line horizontal blanking region statistics module is connected with the input end of the RC ring oscillator circuit controller, the output end of the RC ring oscillator circuit controller is respectively connected with the input ends of the RC ring oscillator and the fixed frequency clock, the output ends of the RC ring oscillator, the fixed frequency clock and the in-line total time monitoring module are respectively connected with the input ends of the clock multiplexing switching circuit, and the output end of the clock multiplexing switching circuit is respectively connected with the input ends of the time sequence adjustment controller and the in-line horizontal blanking region statistics module. The video image receiver is used for receiving and analyzing an original video stream signal, outputting a timing control signal and a data channel signal, the timing adjustment controller is used for alternately reading and writing the data channel signal through two SRAM buffers according to the timing control signal and the video stream processing clock signal generated by the clock multiplexing switching circuit, outputting a video stream and a first data effective identifier, the intra-row horizontal blanking area statistics module is used for counting the first data effective identifier according to the video stream processing clock signal, outputting a numerical value of an intra-row horizontal blanking area, the RC annular oscillation circuit controller is used for adjusting the oscillation frequency of the RC annular oscillator according to the numerical value of the intra-row horizontal blanking area, the RC annular oscillation circuit controller is used for outputting a first clock signal according to the oscillation frequency, the fixed frequency clock is used for outputting a second clock signal, the intra-row total time monitoring module is used for counting the effective pixel area identifier according to a recovered data clock, the intra-row total time reduction identifier is used for outputting a video stream processing clock signal according to the intra-row total time reduction identifier, the intra-row total time reduction identifier is used for indicating that the frame rate keeps stable or increases, the video stream processing clock signal comprises a ref