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CN-116755010-B - Digital I/O channel calibration method for semiconductor test equipment

CN116755010BCN 116755010 BCN116755010 BCN 116755010BCN-116755010-B

Abstract

The invention discloses a digital I/O channel calibration method of semiconductor test equipment, which comprises the steps of S1 grouping the digital I/O channels of the semiconductor test equipment according to at least 3 groups, then testing and solving signal receiving and transmitting delay among the digital I/O channels in each group by using a first calibration board, S2 regrouping the digital I/O channels in a staggered mode by using a '1' mode, then testing and solving the signal receiving and transmitting delay among the digital I/O channels in each regrouped group by using a second calibration board, S3 constructing delay calculation expressions of each digital I/O channel in a transmitting direction and a receiving direction respectively and solving, S4 performing delay compensation on the corresponding digital I/O channels by taking a delay value obtained in the step S3 as a compensation basis, thereby realizing calibration alignment of the digital I/O channels. The invention solves the problem of signal asynchronism between digital I/O channels of test equipment on the premise of not increasing the design difficulty and the manufacturing cost of the calibration plate.

Inventors

  • WANG CONG

Assignees

  • 杭州至千哩科技有限公司

Dates

Publication Date
20260505
Application Date
20220305

Claims (7)

  1. 1. A method for calibrating a digital I/O channel of a semiconductor test apparatus, comprising the steps of: S1, grouping digital I/O channels of semiconductor test equipment into a group according to at least 3, and then testing and solving signal receiving and transmitting delay among the digital I/O channels in each group by using a first calibration board; S2, regrouping the digital I/O channels in a staggered mode of '1' so as to establish a delay calculation relation between groups obtained in the step S1, and then testing and solving signal receiving and transmitting delay between the digital I/O channels in each regrouped group by using a second calibration board; S3, designating the signal delay of any digital I/O channel in the transmitting direction or the receiving direction as a common variable of a delay calculation expression, constructing the delay calculation expression of each digital I/O channel in the transmitting direction and the receiving direction respectively, and solving; S4, performing delay compensation on the corresponding digital I/O channels by taking the delay value obtained in the step S3 as a compensation basis, thereby realizing calibration alignment of the digital I/O channels; The method for testing and solving the signal transceiving delay between the digital I/O channels within each packet by using the first calibration board or the second calibration board is expressed by the following formula (1): In the formula (1), Representing slave digital I/O channels within the same packet Send to digital I/O channel Is a signal reception delay of (1); representing the digital I/O channel Delay in the signal transmission direction; representing the digital I/O channel Delay in the signal reception direction; delay for a test signal from a connector to a PCB trace connection point on the first calibration board or the second calibration board; in step S2, the method for regrouping the groups obtained in step S1 in the manner of error "1" is as follows: s21, sequencing each group obtained in the step S1; S22, after finishing grouping sequencing, sequencing each digital I/O channel in each group to form a sequence arranged in sequence; S23, starting from the second digital I/O channel in the sequence, re-dividing the digital I/O channels of the semiconductor test equipment into a plurality of groups; in step S2, the wiring length of each digital I/O channel in each group divided in the wrong "1" manner between the semiconductor test apparatus and the second calibration board is the same.
  2. 2. The method for calibrating digital I/O channels of semiconductor test apparatus according to claim 1, wherein in step S1, a plurality of digital I/O channels on the test apparatus are divided into a plurality of groups in groups of 3.
  3. 3. The method for calibrating a digital I/O channel of a semiconductor test apparatus according to claim 1, wherein a wiring length of each of the digital I/O channels in each group divided in step S1 is the same between the semiconductor test apparatus and the first calibration board.
  4. 4. The method according to claim 1, wherein in step S23, each of the digital I/O channels of the semiconductor test apparatus is re-divided into several groups in the same grouping unit as step S1 starting from the digital I/O channel of the second ordered in the sequence.
  5. 5. The method of calibrating digital I/O channels of a semiconductor test apparatus according to claim 1, wherein in step S2, a number of said digital I/O channels on said test apparatus are regrouped in groups of 3.
  6. 6. A digital I/O channel calibration method of a semiconductor test apparatus according to claim 3, wherein the wiring length of the digital I/O channel between the semiconductor test apparatus and the first calibration board comprises the wiring length from the I/O interface of the semiconductor test apparatus to a connector and the wiring length from the connector to a PCB trace connection point on the first calibration board; the length of the wiring from each I/O interface to the connector is the same and the length of each wiring led out from the connector and connected to the PCB wiring connection point of the first calibration board is the same.
  7. 7. The method of calibrating a digital I/O channel of a semiconductor test apparatus of claim 1, wherein a wiring length of the digital I/O channel between the semiconductor test apparatus and the second calibration board includes a wiring length from an I/O interface of the semiconductor test apparatus to a connector and a wiring length from the connector to a PCB trace connection point on the second calibration board; The length of the wiring from each I/O interface to the connector is the same and the length of each wiring led out from the connector and connected to the PCB wiring connection point of the second calibration board is the same.

Description

Digital I/O channel calibration method for semiconductor test equipment Technical Field The invention relates to the technical field of I/O channel calibration, in particular to a digital I/O channel calibration method of semiconductor test equipment. Background In the field of semiconductor testing, for digital chips such as Application SPECIFIC INTEGRATED Circuit (Application specific integrated Circuit), memory chip and the like, test equipment is connected to tested pins of the chip by providing digital I/O channels and gives excitation signals meeting time sequence requirements or receives signals from the tested chip, so that the purposes of testing chip functions, time sequence parameters and the like are achieved. The digital I/O channels provided by the test equipment are generally more, and the delay of signals sent to the tested chip from the I/O channels or the delay of signals received from the tested chip are required to be equal or have a fixed difference in the test process, so that the receiving and sending of test signals can be synchronous, and particularly for the test of parallel interfaces, for example, when testing DDR chips, the time sequence requirements between the signals can be accurately controlled. Therefore, in order to achieve equal or fixed delay between the I/O channels, the I/O channels need to be calibrated before the test equipment leaves the factory, the delay of the signals sent from the I/O channels to the tested chip or the delay of the signals received from the tested chip is measured and compensated into the delay circuit of the signal sending or receiving, so as to achieve the synchronization of signal sending and receiving between the channels. In the conventional general I/O channel calibration method, as shown in fig. 1, a calibration board 1 is designed to measure signal delay in a transmission direction of a digital I/O channel, a TDC (Time-to-Digital Converter, i.e., a Time-to-digital converter, which is a commonly used Time interval measurement electronic circuit, and a commonly used high-precision Time measurement chip has a TDC-GP2, etc.) chip is used on the calibration board 1 to test signal delay between different I/O channels (the numbers "1" and "2" in fig. 1 respectively represent the I/O channels 1 and 2 on a test device). The calibration board 2 is used for measuring signal delay in the receiving direction of the digital I/O channel, a synchronous signal Generator is adopted on the calibration board 2 to send out synchronous signals with phase alignment, and a TG (Timing Generator, generally implemented by an FPGA chip) measures the signal delay in the receiving direction. Finally, delay compensation is performed according to the measured signal delay in the two directions of transmission and reception between the I/O channels, so that the signals are synchronous. However, the existing I/O channel calibration method has the following two technical problems: 1. The calibration plate is complex in design, the number of TDC and synchronization signal generators on the calibration plate is limited, and the number of channels on a single TDC chip and synchronization signal generator is also limited, typically 4, 8 or 16. Therefore, in the case of a large number of I/O channels, a larger number of TDC chips and synchronization signal generators need to be arranged on the calibration board, increasing the design difficulty and manufacturing cost of the calibration board. 2. Signal synchronization is also required between a plurality of TDC chips or between a plurality of synchronous signal generators on the calibration plate, the synchronization needs a uniform reference source REF_CLK, one or more stages of synchronous signal generators are added to the TDC chips for measuring delay or the generators for generating synchronous signals, and although the synchronism between signals generated by each synchronous signal generator is higher, a certain synchronous error exists, and the error is amplified through multistage accumulation, so that the calibration precision of the calibration plate is affected. Disclosure of Invention The invention provides a digital I/O channel calibration method of semiconductor test equipment, which aims to solve the problem of signal dyssynchrony between I/O channels of the test equipment on the premise of not increasing the design difficulty and the manufacturing cost of a calibration board. To achieve the purpose, the invention adopts the following technical scheme: there is provided a digital I/O channel calibration method for a semiconductor test apparatus, comprising the steps of: S1, grouping digital I/O channels of semiconductor test equipment into a group according to at least 3, and then testing and solving signal receiving and transmitting delay among the digital I/O channels in each group by using a first calibration board; S2, regrouping the digital I/O channels in a staggered mode of '1' so as to establish a delay