CN-116755137-B - NMOS-based stepped nuclear radiation total dose indication and compensation circuit

CN116755137BCN 116755137 BCN116755137 BCN 116755137BCN-116755137-B

Abstract

The step bias switching circuit receives an NMOS transistor induction signal and switches the bias voltage to an NMOS transistor radiation induction array circuit, the induction array circuit indicates the total ionizing radiation dosage level of a circuit board through radiation damage of a nuclear radiation source to an NMOS transistor, the FPGA compensation control circuit receives a level change signal output from the induction array circuit and outputs a nuclear radiation total dose of corresponding size, the digital potentiometer outputs a compensation control signal, and the digital potentiometer is modified to compensate the radiation damage electric signal output resistance. The invention evaluates the fixed point size of the total radiation dose of the current circuit board in the nuclear radiation environment by utilizing the threshold voltage radiation damage effect of the NMOS transistor, provides an indication signal for the FPGA radiation compensation circuit, and has the advantages of low power consumption, strong robustness and the like.

Inventors

JIANG CHAO
QIU TIAN
WANG ZHONGHUA

Assignees

湖南大学

Dates

Publication Date: 20260512
Application Date: 20230517

Claims (5)

1. An NMOS-based stepped total nuclear radiation dose indication and compensation circuit, comprising: A bias voltage circuit, a step bias switching circuit, an NMOS transistor radiation induction array circuit and an FPGA compensation control circuit, The bias circuit is formed by connecting a plurality of resistors in series, the voltage division of each resistor provides a step-type bias voltage for the grid electrode of an NMOS tube in the NMOS transistor radiation induction array circuit, the step-type bias voltage is switched by the step bias switching circuit, and the bias voltage is controlled by adjusting the size of the resistor; The step bias switching circuit receives an NMOS transistor induction signal from the NMOS transistor radiation induction array circuit and switches bias voltage to the NMOS transistor radiation induction array circuit; the NMOS transistor radiation induction array circuit indicates the total ionizing radiation dosage level of the circuit board through radiation damage of the nuclear radiation source to the NMOS transistor of the NMOS transistor radiation induction array circuit; The FPGA compensation control circuit consists of an FPGA basic unit and a digital potentiometer, wherein the FPGA basic unit receives level change signals output by the NMOS transistor radiation induction array circuit and outputs nuclear radiation total dose with corresponding size according to different IO ports with level change; The NMOS transistor radiation induction array circuit is formed by connecting a plurality of NMOS transistors in parallel, wherein the grid electrode is connected with the nominal voltage divided by a bias resistor or is directly grounded, the switching logic is controlled by a step bias switching circuit, the drain electrode is connected with a control selection port of the step bias switching circuit, the high level is stabilized by a pull-up resistor, the source electrode is directly grounded, the grid electrode of a first NMOS transistor in the NMOS transistors is directly connected with the set starting voltage, the drain electrode of the NMOS transistor radiation induction array circuit is subjected to level change by nuclear radiation, and the drain electrode is connected to an IO port of an FPGA compensation control circuit in parallel.
2. The circuit of claim 1, wherein the series resistance of the bias voltage circuit is determined by a measured voltage, a first NMOS transistor gate of the NMOS transistor radiation sensing array circuit is connected to a start bias voltage provided by two voltage dividing resistors, the voltage dividing resistors are lower than a normal NMOS transistor threshold voltage, and the remaining resistors are pull-up resistors connected to drains of the remaining NMOS transistor array.
3. The circuit of claim 1, wherein the ladder bias switching circuit is comprised of a plurality of one-out-of-two analog switching circuits, a first data port is connected to a corresponding NMOS transistor gate in the NMOS transistor radiation sensing array circuit, a second data port B0 is connected to a divided calibration voltage provided by the bias voltage circuit, a third data port is connected to ground, a control select port is connected to a corresponding NMOS transistor drain in the NMOS transistor radiation sensing array circuit, the first data port is connected to the second data port when the control select port is at a low level, and the first data port is connected to the third data port when the data select port is at a high level.
4. The circuit of claim 1, wherein after the FPGA basic unit receives the potential change signal of the NMOS transistor radiation sensing array circuit, the FPGA basic unit calculates the corresponding total nuclear radiation dose through the table look-up unit and outputs the calculated total nuclear radiation dose as a digital signal, and at the same time, the FPGA basic unit inputs the total nuclear radiation dose value into the internal BP network forward calculation unit and outputs the calculated total nuclear radiation dose value to obtain the corresponding electrical parameter offset value of the radiation damage electrical signal, the output resistance of the radiation damage electrical signal is controlled by the digital potentiometer, the offset value to be compensated outputs the digital signal through the FPGA basic unit, and the resistance value of the digital potentiometer is controlled to compensate the radiation damage signal.
5. The circuit of claim 4, wherein the BP network forward calculation unit builds and trains the BP neural network by taking the total nuclear radiation dose and the electrical parameter offset value of the radiation damage signal as training data, wherein the electrical parameter offset value is the amplitude difference value between the radiation damage signal of the sensor and the normal signal, the value output by the BP neural network is a modified value of a digital potentiometer, the weight obtained by training the BP neural network is stored into an on-chip RAM of the FPGA basic unit after being transcoded, the total nuclear radiation dose obtained by the table look-up unit is input into the BP neural network, and the digital potentiometer is controlled to compensate the amplitude of the radiation damage signal after the electrical parameter offset value of the radiation damage signal is obtained and output.

Description

NMOS-based stepped nuclear radiation total dose indication and compensation circuit Technical Field The invention relates to the technical field of nuclear radiation safety monitoring, in particular to a step-type nuclear radiation total dose indication and compensation circuit based on NMOS. Background As nuclear power becomes one of the main power generation modes, the safety of the nuclear power station with radioactivity is attracting attention, the nuclear emergency rescue equipment and method become research hotspots, and the demand for the nuclear emergency treatment robot is growing. The nuclear environment operation robot can effectively reduce the damage of the nuclear radiation environment to operators, and the most critical of the service of the robot system in the nuclear radiation environment is how to overcome the radiation damage effect of the circuit system, and the circuit system is easily influenced by the ionization total dose effect in the nuclear radiation environment, so that the circuit system cannot work normally, and the whole robot system is paralyzed. The existing treatment of the total ionizing radiation dose effect of the circuit system is mainly divided into three types, namely radiation resistance reinforcement is carried out on a semiconductor material, and the radiation influence is reduced by utilizing methods of changing oxide impurities, oxide layer defects, oxide layer structures and the like. The second type is a radiation-resistant circuit and layout reinforcement design for an integrated circuit, threshold voltage drift and edge leakage current are caused by accumulation of trap charges induced by radiation in an oxide layer, and potential leakage current channels are cut off by modifying circuit and device layout structures. The radiation-resistant reinforcement design of the two types of circuit systems requires a great deal of resources to be put into research, and the cost is extremely high. The third type of circuit system structure is generally adopted to improve the radiation resistance, the general method is to improve the robustness of the circuit system, a certain evaluation is needed to be carried out on the current radiation dose to improve the adaptability of the circuit system, the general radiation dose indicator instrument circuit is complex, and the weak signal amplification module is required to be additionally reinforced against radiation. There is therefore a need for an efficient total ionizing radiation dose indication circuit and effective compensation of radiation damaged electrical signals. Disclosure of Invention The invention designs an NMOS-based stepped nuclear radiation total dose indication and compensation circuit, which comprises: A bias voltage circuit, a step bias switching circuit, an NMOS transistor radiation induction array circuit and an FPGA compensation control circuit, The bias circuit is formed by connecting a plurality of resistors in series, the voltage division of each resistor provides a step-type bias voltage for the grid electrode of an NMOS tube in the NMOS transistor radiation induction array circuit, the step-type bias voltage is switched by the step bias switching circuit, and the bias voltage is controlled by adjusting the size of the resistor; The step bias switching circuit receives an NMOS transistor induction signal from the NMOS transistor radiation induction array circuit and switches bias voltage to the NMOS transistor radiation induction array circuit; the NMOS transistor radiation induction array circuit indicates the total ionizing radiation dosage level of the circuit board through radiation damage of the nuclear radiation source to the NMOS transistor of the NMOS transistor radiation induction array circuit; The FPGA compensation control circuit comprises an FPGA basic unit and a digital potentiometer, wherein the FPGA basic unit receives level change signals output by the NMOS transistor radiation induction array circuit, outputs nuclear radiation total dose with corresponding size according to different IO ports with level change, outputs compensation control signals to the digital potentiometer, and compensates radiation damage electric signal output resistance by modifying the digital potentiometer. Further, the series resistance of the bias voltage circuit is determined by the measured voltage, the gate of the first NMOS transistor of the NMOS transistor radiation sensing array circuit is connected with the starting bias voltage provided by two voltage dividing resistors, the voltage dividing voltage of the resistor is lower than the threshold voltage of the normal NMOS transistor, and the rest resistors are pull-up resistors connected with the drain electrodes of the rest NMOS transistor arrays. Further, the step bias switching circuit is composed of a plurality of alternative analog switch circuits, a first data port is connected with a corresponding NMOS transistor grid electrode in the NMOS tr