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CN-116799889-B - Power saving system of battery charger

CN116799889BCN 116799889 BCN116799889 BCN 116799889BCN-116799889-B

Abstract

The invention provides a power saving system of a battery charger. The control terminal of the first transistor receives a wake-up signal. The counter is connected to the first end of the first transistor. The counter judges whether the duty cycle of the wake-up signal received from the first transistor is greater than a time threshold value to output a count signal. When the counting signal indicates that the working period of the wake-up signal is not more than the time threshold value, the counter is turned off, and a plurality of electronic components of the electronic device are kept off so as to save the power of the battery. When the counting signal indicates that the working period of the wake-up signal is larger than the time threshold, the electronic device is switched from the power saving mode to the normal operation mode, and the battery can supply power to the electronic device.

Inventors

  • CHEN ZHINING
  • Su Chiheng

Assignees

  • 茂达电子股份有限公司

Dates

Publication Date
20260505
Application Date
20220325
Priority Date
20220317

Claims (15)

  1. 1. A power saving system of a battery charger, the power saving system of the battery charger comprising: a control end of the first transistor is connected with an external power supply circuit to receive a wake-up signal from the external power supply circuit, and a first end of the first transistor is coupled with an input voltage; a first end and a control end of the second transistor are connected with a second end of the first transistor, and a second end of the second transistor is grounded; A counter, a trigger end of the counter is connected with the first end of the first transistor, when the counter receives the wake-up signal from the first transistor in a power-saving mode and is waken by the wake-up signal, the counter judges whether the working period of the wake-up signal is larger than a time threshold value so as to output a counting signal, and An operation management circuit connecting the counter and an electronic device coupled to a battery, the operation management circuit configured to receive the count signal from the counter; Wherein when the operation management circuit receives the count signal in the power saving mode to indicate that the working period of the wake-up signal is not more than the time threshold, the operation management circuit turns off the counter and keeps turning off a plurality of electronic components contained in the electronic device; When the operation management circuit receives the counting signal in the power saving mode and indicates that the working period of the wake-up signal is larger than the time threshold, the operation management circuit decides that the battery is switched from the power saving mode to a normal operation mode, and triggers the electronic device to start and receive the power of the external power supply circuit or the battery.
  2. 2. The power saving system of claim 1 further comprising a first resistor, a first terminal of the first resistor being connected to the control terminal of the first transistor, a second terminal of the first resistor being grounded.
  3. 3. The power saving system of claim 1, further comprising a current source having a first terminal coupled to the input voltage and a second terminal coupled to the first terminal of the first transistor.
  4. 4. The power saving system of claim 3 further comprising a third transistor and an input resistor, the first terminal of the third transistor and the first terminal of the input resistor being connected to the cathode of a first diode and the cathode of a second diode, the anode of the first diode being connected to the battery, the anode of the second diode being connected to the external power supply circuit, the second terminal of the input resistor being connected to the control terminal of the third transistor, the second terminal of the third transistor being connected to the current source, the voltage of the second terminal of the third transistor being the input voltage.
  5. 5. The power saving system of claim 4, further comprising a fourth transistor and a fifth transistor, wherein a first terminal of the fourth transistor is connected to the second terminal of the input resistor and the control terminal of the fourth transistor, wherein a second terminal of the fourth transistor is connected to the first terminal of the fifth transistor and the control terminal of the fifth transistor, and wherein a second terminal of the fifth transistor is grounded.
  6. 6. The power saving system of claim 4 further comprising a first inverter, an input of the first inverter being connected to a first terminal of the first transistor, an output of the first inverter being connected to the trigger terminal of the counter, a positive power terminal of the first inverter being connected to a second terminal of the third transistor, a negative power terminal of the first inverter being grounded.
  7. 7. The power saving system of claim 6, further comprising a voltage detection circuit coupled to the second terminal of the third transistor and configured to detect whether the voltage at the second terminal of the third transistor is greater than a voltage threshold to output a voltage detection signal.
  8. 8. The power saving system of claim 7, further comprising a first edge trigger circuit, wherein a power supply terminal of the first edge trigger circuit is connected to the second terminal of the third transistor, an input terminal of the first edge trigger circuit is connected to the output terminal of the voltage detection circuit, and the first edge trigger circuit determines a level of a first trigger signal according to the voltage detection signal and outputs the first trigger signal.
  9. 9. The power saving system of claim 8, further comprising a first flip-flop having a power supply terminal coupled to the second terminal of the third transistor, a first input terminal coupled to the output terminal of the first edge trigger circuit, and an output terminal coupled to the enable terminal of the counter.
  10. 10. The power saving system of claim 9 further comprising a first or gate and a second inverter, wherein an input of the second inverter is connected to an output of the voltage detection circuit and receives the voltage detection signal, an output of the second inverter is connected to a first input of the first or gate, a second input of the first or gate is connected to an output of the counter, and an output of the first or gate is connected to a second input of the first positive and negative inverter.
  11. 11. The power saving system of claim 10, further comprising a second or gate, wherein a first input of the second or gate is connected to the output of the counter, a second input of the second or gate is connected to an output of a control circuit, and an output of the second or gate is connected to the second input of the first or gate, the control circuit determining whether the battery is switched from the normal operation mode to the power saving mode to output a control signal to the second input of the second or gate.
  12. 12. The power saving system of claim 11, further comprising a memory circuit having an input coupled to the output of the control circuit and an output coupled to the second input of the second or gate.
  13. 13. The power saving system of claim 12, further comprising a third or gate and a second flip-flop, wherein a first input of the third or gate is connected to an output of the second or gate, a second input of the third or gate is connected to an output of the second inverter, an output of the third or gate is connected to a first input of the second flip-flop, a power supply of the second flip-flop is connected to a second end of the third transistor, and an output of the second flip-flop is connected to an input of the operation management circuit.
  14. 14. The power saving system of claim 13, further comprising an and gate having a first input connected to the output of the voltage detection circuit and receiving the voltage detection signal, a second input connected to the output of the first inverter, a fourth or gate having a first input connected to the output of the first edge trigger circuit, a second input connected to the output of the and gate, and an output connected to the second input of the second flip-flop.
  15. 15. The power saving system of claim 14 further comprising a second edge trigger circuit, a power supply terminal of the second edge trigger circuit being connected to the second terminal of the third transistor, an input terminal of the second edge trigger circuit being connected to the output terminal of the first inverter, and an output terminal of the second edge trigger circuit being connected to the second input terminal of the and gate.

Description

Power saving system of battery charger Technical Field The present invention relates to battery chargers, and more particularly, to a power saving system for a battery charger. Background With rapid development of electronic technology, various electronic products such as mobile phones, desktop computers, notebook computers, etc. are widely used in daily life of people. Most of these electronic products use rechargeable batteries as energy sources. Whenever the power of the electronic product is insufficient, the rechargeable battery can provide the power required by the operation of the electronic product at any time. However, during transportation of the electronic product, for example, during shipping, when the electronic product is not in use, the battery continuously supplies power to the electronic product, which causes unnecessary power consumption of the battery. Disclosure of Invention The invention aims to solve the technical problem of providing a power saving system of a battery charger, which aims to overcome the defects of the prior art and comprises a first transistor, a second transistor, a counter and an operation management circuit. The control end of the first transistor is connected with an external power circuit to receive a wake-up signal from the external power circuit. The first end of the first transistor is coupled to the input voltage. The first terminal and the control terminal of the second transistor are connected to the second terminal of the first transistor. The second terminal of the second transistor is grounded. The trigger end of the counter is connected with the first end of the first transistor. When the counter receives the wake-up signal from the first transistor in the power saving mode and is awakened by the wake-up signal, the counter judges whether the working period of the wake-up signal is larger than a time threshold value or not so as to output a counting signal. The operation management circuit is connected with the counter and the electronic device. The electronic device is coupled with the battery. The operation management circuit is configured to receive a count signal from the counter. When the operation management circuit receives the counting signal in the power saving mode and indicates that the working period of the wake-up signal is not more than the time threshold, the operation management circuit turns off the counter and keeps turning off a plurality of electronic components contained in the electronic device. When the operation management circuit receives the counting signal in the power saving mode to indicate that the working period of the wake-up signal is larger than the time threshold, the operation management circuit determines that the battery is switched from the power saving mode to the normal operation mode, and triggers the electronic device to start and receive the power of the external power supply circuit or the battery. In an embodiment, the power saving system of the battery charger further comprises a first resistor. The first end of the first resistor is connected with the control end of the first transistor. The second end of the first resistor is grounded. In an embodiment, the power saving system of the battery charger further comprises a current source. The first terminal of the current source is coupled to the input voltage. The second terminal of the current source is connected to the first terminal of the first transistor. In an embodiment, the power saving system of the battery charger further comprises a third transistor and an input resistor. The first end of the third transistor and the first end of the input resistor are connected with the cathode of the first diode and the cathode of the second diode. The anode of the first diode is connected with the battery. The anode of the second diode is connected with an external power circuit. The second end of the input resistor is connected with the control end of the third transistor. The second end of the third transistor is connected with a current source. The voltage of the second end of the third transistor is the input voltage. In an embodiment, the power saving system of the battery charger further includes a fourth transistor and a fifth transistor. The first end of the fourth transistor is connected with the second end of the input resistor and the control end of the fourth transistor. The second end of the fourth transistor is connected with the first end of the fifth transistor and the control end of the fifth transistor, and the second end of the fifth transistor is grounded. In an embodiment, the power saving system of the battery charger further comprises a first inverter. The input end of the first inverter is connected with the first end of the first transistor. The output end of the first inverter is connected with the trigger end of the counter. The positive power supply terminal of the first inverter is connected to the second terminal of the third trans