CN-116930842-B - Hall chip calibration structure, method, system, device and Hall chip

CN116930842BCN 116930842 BCN116930842 BCN 116930842BCN-116930842-B

Abstract

The embodiment of the invention provides a Hall chip calibration structure, a Hall chip calibration method, a Hall chip calibration system, a Hall chip calibration device and a Hall chip, and belongs to the technical field of chips. The Hall chip calibration structure comprises at least one checking Hall disc, wherein the appearance of the checking Hall disc is the same as that of a Hall disc used for realizing functions in a Hall chip to be calibrated, the checking Hall disc is provided with an input end and an output end, the input end of the checking Hall disc is connected with an externally excited output end, and the output end of the checking Hall disc is used for outputting Hall voltage. Compared with the prior art that a circuit or a module is adopted for calibration, the calibration error is greatly reduced, and the accuracy of a calibration result is improved.

Inventors

LI PEIXIAO
LI LIANG
DU JUN
WANG XIANG
JIANG SHUAI
WANG HAO
FANG DONGMING
SUN HENGCHAO
Ji Runke
TAO YI
WANG MANRONG
WEN ZHIGUO

Assignees

北京智芯微电子科技有限公司
北京智芯半导体科技有限公司

Dates

Publication Date: 20260505
Application Date: 20230712

Claims (14)

1. The Hall chip calibration structure is characterized by comprising at least one checking Hall disc, wherein the appearance of the checking Hall disc is the same as that of a Hall disc used for realizing functions in a Hall chip to be calibrated; The Hall chip calibration structure is arranged in the Hall chip to be calibrated, the verification Hall disc forms a calibration area, the verification Hall disc in the calibration area is a Hall effect area, external excitation is input to the verification Hall disc and the Hall chip to be calibrated at the same time when calibration is carried out, when constant voltage bias is carried out, output Hall voltage is proportional to the length-width ratio of the Hall effect area, zero bias is calculated according to the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure to obtain a zero bias calibration value, an ideal Hall voltage output ratio is determined according to the appearance of the verification Hall disc in the Hall chip calibration structure and the appearance of the Hall disc in the Hall chip to be calibrated, and a temperature drift calibration value is determined based on the ideal Hall voltage output ratio, the voltage value of the Hall chip to be calibrated, the voltage value of the Hall chip calibration structure and the zero bias calibration value.
2. The hall chip calibration structure of claim 1, wherein the check hall plate has a plurality of PADs connected thereto, the plurality of PADs serving as an input terminal and an output terminal of the check hall plate, respectively.
3. The hall chip calibration structure of claim 1, wherein the outline of the verification hall plate comprises a rectangle, a square, a cross, and an octagon.
4. The hall chip calibration structure of claim 1, wherein there is a proportional relationship between the size of the calibration hall disc and the size of the hall disc for function implementation in the hall chip to be calibrated.
5. The hall chip calibration structure of claim 1, wherein the number of the verification hall plates is plural, and the sizes of the respective verification hall plates are the same or different.
6. The Hall chip calibration structure according to claim 1, wherein the appearance of the verification Hall disk and the appearance of the Hall disk for realizing functions in the Hall chip to be calibrated are rectangular, the width of the verification Hall disk is identical to the width of the Hall disk for realizing functions in the Hall chip to be calibrated, and the length of the verification Hall disk and the length of the Hall disk for realizing functions in the Hall chip to be calibrated have a proportional relationship.
7. The hall chip calibration structure of claim 6, wherein the plurality of verification hall plates are different in length.
8. A hall chip comprising a hall disc structure for functional implementation and a hall chip calibration structure according to any one of claims 1-7.
9. The hall chip of claim 8, further comprising a conditioning circuit chip, an input of the conditioning circuit chip being connected to an output of the hall disk chip.
10. The Hall chip calibration system is characterized by comprising a conditioning circuit chip and the Hall chip as claimed in claim 8, wherein the output end of the Hall chip is connected with the input end of the conditioning circuit chip, and the input end of the Hall chip is connected with the output end of external excitation.
11. A hall chip calibration method, characterized by being applied to the hall chip calibration structure of any one of claims 1 to 7, comprising: Under the condition that excitation is applied to the Hall chip to be calibrated and the Hall chip calibration structure, respectively acquiring a voltage value of the Hall chip to be calibrated and a voltage value of the Hall chip calibration structure; obtaining a calibration value based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure; Wherein the calibration values include Wen Piaojiao calibration values and zero calibration values; The obtaining the calibration value based on the voltage value of the hall chip to be calibrated and the voltage value of the hall chip calibration structure comprises the following steps: Calculating zero offset according to the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure to obtain a zero offset calibration value; acquiring a zero offset calibration value; Determining an ideal Hall voltage output ratio according to the appearance of the verification Hall disc in the Hall chip calibration structure and the appearance of the Hall disc in the Hall chip to be calibrated; And determining and obtaining a temperature drift calibration value based on the ideal Hall voltage output ratio, the voltage value of the Hall chip to be calibrated, the voltage value of the Hall chip calibration structure and the zero offset calibration value.
12. A hall chip calibration apparatus, characterized by being applied to the hall chip calibration structure according to any one of claims 1 to 8, comprising: The acquisition module is used for respectively acquiring the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure under the condition that excitation is applied to the Hall chip to be calibrated and the Hall chip calibration structure; The calibration module is used for obtaining a calibration value based on the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure; Wherein the calibration values include Wen Piaojiao calibration values and zero calibration values; The calibration module includes: The zero offset calibration unit is used for calculating zero offset according to the voltage value of the Hall chip to be calibrated and the voltage value of the Hall chip calibration structure to obtain a zero offset calibration value; the zero offset acquisition unit is used for acquiring a zero offset calibration value; The ratio determining unit is used for determining an ideal Hall voltage output ratio of each checking Hall disc based on the appearance of the checking Hall disc in the Hall chip calibrating structure and the appearance of the Hall disc in the Hall chip to be calibrated; The calculating unit is used for determining and obtaining a temperature drift calibration value based on the ideal Hall voltage output ratio of each checking Hall disc, the voltage value of the Hall chip to be calibrated, the voltage value of the Hall chip calibration structure and the zero offset calibration value.
13. A processor configured to perform the hall chip calibration method of claim 11.
14. A machine-readable storage medium having instructions stored thereon, which when executed by a processor cause the processor to be configured to perform the hall chip calibration method of claim 11.

Description

Hall chip calibration structure, method, system, device and Hall chip Technical Field The invention relates to the technical field of chips, in particular to a Hall chip calibration structure, a Hall chip calibration method, a Hall chip calibration device, a Hall chip calibration system, a Hall chip, a machine-readable storage medium and a processor. Background Hall effect semiconductors are used for hall chips. Hall effect refers to the physical phenomenon of a magnetic field being applied to the lateral potential difference between a current carrying semiconductor and a current carrier in a metal conductor. A common hall chip includes a hall current sensor. When the existing Hall chip is calibrated, a calibration device is mostly built outside the Hall chip, for example, the calibration device comprises a calibration winding, a zero detection coil, a calibration current source and an excitation current detector, two ends of the excitation current detection winding are respectively connected with the excitation current detector so that the excitation current detector measures the current of the excitation current detection winding, the excitation current detector adjusts the output current of the calibration current source according to the measured current of the excitation current detection winding, and online zero calibration can be carried out on the Hall current sensor. The calibration is realized by constructing the calibration device outside the Hall chip, and the calibration device is usually composed of a circuit or a module, so that errors exist in the calibration device, and the calibration is inaccurate. Disclosure of Invention The embodiment of the invention aims to provide a Hall chip calibration structure, a Hall chip calibration method, a Hall chip calibration device, a Hall chip calibration system, a Hall chip, a machine-readable storage medium and a processor. In order to achieve the purpose, the first aspect of the application provides a Hall chip calibration structure, which comprises at least one checking Hall disc, wherein the appearance of the checking Hall disc is the same as that of a Hall disc used for realizing functions in a Hall chip to be calibrated, the checking Hall disc is provided with an input end and an output end, the input end of the checking Hall disc is connected with an externally excited output end, and the output end of the checking Hall disc is used for outputting Hall voltage. In the embodiment of the application, the Hall chip calibration structure is arranged in the Hall chip to be calibrated. In the embodiment of the application, the verification hall disc is connected with a plurality of PADs, and the PADs are respectively used as an input end and an output end of the verification hall disc. In the embodiment of the application, the outline of the verification hall disc comprises a rectangle, a square, a cross and an octagon. In the embodiment of the application, a proportional relationship exists between the size of the verification hall disc and the size of the hall disc used for realizing functions in the hall chip to be calibrated. In the embodiment of the application, the number of the verification hall discs is multiple, and the sizes of the verification hall discs are the same or different. In the embodiment of the application, the appearance of the verification Hall disc and the appearance of the Hall disc used for realizing functions in the Hall chip to be calibrated are rectangular, wherein the width of the verification Hall disc is the same as the width of the Hall disc used for realizing functions in the Hall chip to be calibrated, and the length of the verification Hall disc and the length of the Hall disc used for realizing functions in the Hall chip to be calibrated have a proportional relationship. In the embodiment of the application, the number of the verification hall discs is multiple, and the lengths of the verification hall discs are different. The second aspect of the application provides a Hall chip, which comprises a Hall disc chip, wherein the Hall disc chip comprises a Hall disc structure for realizing functions and the Hall chip calibration structure. In the embodiment of the application, the Hall disc comprises a Hall disc chip, and the Hall disc chip is connected with the Hall disc chip. The application provides a Hall chip calibration system which is characterized by comprising a conditioning circuit chip and the Hall chip, wherein the output end of the Hall chip is connected with the input end of the conditioning circuit chip, and the input end of the Hall chip is connected with the output end of external excitation. A fourth aspect of the present application provides a hall chip calibration method, which is applied to the above hall chip calibration structure, including: Under the condition that excitation is applied to the Hall chip to be calibrated and the Hall chip calibration structure, respectively acquiring a voltage val