CN-116931810-B - Data refreshing method and controller for flash memory

Abstract

The application discloses a data refreshing method and a controller for a flash memory. The data refreshing method comprises the steps of dividing a physical block of the flash memory into a plurality of sub-blocks through a reliability test, obtaining a reliability influence type of the physical block according to a read retry operation, obtaining a first reliability level of the plurality of sub-blocks of the physical block according to the reliability influence type of the physical block, obtaining a second reliability level of different types of logic pages of the physical block according to the reliability influence type of the physical block, sorting the plurality of logic pages of the physical block according to the first reliability level and the second reliability level, and moving the plurality of logic pages of the physical block according to the sorting. The data refreshing method adopts a mode of partitioning and moving logical pages of physical blocks to improve the data reliability of the flash memory in the data refreshing process.

Inventors

• CAO RUI
• YU XIAOFAN
• XIAO ZIHUA

Assignees

• 联芸科技(杭州)股份有限公司

Dates

Publication Date

20260512

Application Date

20220330

Claims (19)

1. 1. A data refresh method for a flash memory, comprising: dividing a physical block of the flash memory into a plurality of sub-blocks through a reliability test; Obtaining the reliability influence type of the physical block according to the read retry operation; Obtaining a first reliability level of a plurality of sub-blocks of the physical block according to the reliability influence type of the physical block; Obtaining a second reliability level of different types of logic pages of the physical block according to the reliability influence type of the physical block; Ordering a plurality of logical pages of the physical block according to the first reliability level and the second reliability level, and Based on the ordering, the plurality of logical pages of the physical block are moved in a low to high order of reliability level, Wherein the sorting comprises sequentially performing the steps of: Ordering the plurality of logical pages of the physical block according to a second level of reliability of different types of logical pages of the physical block, and For a plurality of logical pages of a particular type, ordering is performed according to a first reliability level of a plurality of sub-blocks of the physical block.
2. 2. The data refresh method of claim 1, wherein the reliability test comprises at least one of: Performing a program/erase cycle operation on the physical block; data retention testing in a high temperature environment, and And performing a read interference test in a normal temperature environment.
3. 3. The data refresh method of claim 1, wherein the reliability test obtains threshold voltage distributions and/or bit error rate distributions for a plurality of physical pages in the physical block.
4. 4. A data refreshing method according to claim 3, wherein the physical block is divided into a plurality of sub-blocks having different reliability levels according to a threshold voltage distribution and/or an error rate distribution.
5. 5. The data refresh method of claim 4, wherein a reliability test is performed multiple times during use of the flash memory to dynamically adjust the number of sub-block areas and sub-blocks in the physical block.
6. 6. The data refresh method of claim 1, wherein the read retry operation includes selecting a new set of read threshold voltages according to a retry table and performing a read operation with the new set of read threshold voltages to identify a state of charge in a memory cell.
7. 7. The data refresh method of claim 6, wherein the reliability impact type includes at least one of a retention time impact and a read disturb impact.
8. 8. The data refresh method of claim 7, wherein the retention time effect is determined to be present in the event that a read threshold voltage of a programmed highest state of the physical block is less than a reference value.
9. 9. The data refresh method of claim 7, wherein the read disturb effect is determined to be present in the event that a read threshold voltage of a programmed lowest state of the physical block is greater than a reference value.
10. 10. The data refresh method of claim 7, wherein the order of the first reliability levels of the plurality of sub-blocks is opposite to each other in a case where the reliability impact type is a retention time impact than in a case where the reliability impact type is a read disturb impact.
11. 11. The data refresh method of claim 7, wherein an order of second reliability levels of the different types of logical pages is different from each other in a case where the reliability impact type is a retention time impact than in a case where the reliability impact type is a read disturb impact.
12. 12. The data refresh method of claim 7, wherein, in the case where the reliability impact type is a retention time impact, the second reliability level of the different types of logical pages of the physical block is incremented in the order of top page, and bottom page.
13. 13. The data refresh method of claim 7, wherein, in the case where the reliability impact type is a read disturb effect, the second reliability level of the different types of logical pages of the physical block is incremented in the order of lower page, top page, and upper page.
14. 14. The data refresh method of claim 7, wherein in the case where the reliability impact type is a retention time impact and a read disturb impact, the second reliability level of the different types of logical pages of the physical block is incremented in the order of top page, bottom page, and top page.
15. 15. The data refresh method of claim 14, wherein for a plurality of logical pages of a top page type, ordering is by a first level of reliability of a plurality of sub-blocks of the physical block in the event of a data retention impact.
16. 16. The data refresh method of claim 14, wherein for a plurality of logical pages of a lower page type, ordering is by a first level of reliability of a plurality of sub-blocks of the physical block in the event of read disturb effects.
17. 17. The data refresh method of claim 14, wherein for a plurality of logical pages of an upper page type, ordering is performed according to a first level of reliability of a plurality of sub-blocks of the physical block in the event of a data retention impact.
18. 18. The data refresh method of claim 1, wherein the flash memory includes a plurality of physical blocks, and the data refresh method is performed by selecting a physical block according to an error rate of the plurality of physical blocks.
19. 19. A controller for a flash memory, comprising: The cache chip is used for storing the physical block of the flash memory, the sub-block information of the physical block and the reliability influence type information of the physical block; a memory controller connected with the flash memory, the memory controller providing data transmission and data read/write functions, and A processor, coupled to the cache chip and the memory controller, for performing the data refresh method according to any one of claims 1 to 18.

Description

Data refreshing method and controller for flash memory Technical Field The present invention relates to the field of data storage technologies, and in particular, to a data refreshing method and a controller for a flash memory. Background The Solid state disk (Solid STATE DRIVES) is a storage hard disk made of Solid state electronic storage chips, and mainly comprises a controller, a storage medium and a cache chip. Currently, the most popular solid state disk uses a Flash Memory (Flash Memory) as a storage medium to store data, such as a nonvolatile Memory as an example of NAND Flash Memory. In a flash memory, a gate structure of a memory cell includes a tunneling dielectric layer, a floating gate, a gate dielectric layer, and a control gate, which are stacked in sequence. When a program voltage is applied to the control gate, charge is injected into the floating gate by tunneling to effect programming, and when an erase voltage is applied to the control gate, charge is removed from the floating gate by tunneling to effect erasing. The read voltage is applied to the control gate and the amount of charge in the floating gate can be taken up with the threshold voltage of the memory cell to effect the read. In the off state of the flash memory, charge in the floating gate can be maintained due to the insulating effect of the tunneling dielectric layer. Due to physical structure limitations of flash memory, voltages are applied not only to selected memory cells but also to adjacent memory cells in read, program and erase operations of flash memory. Data errors of the memory cells may be caused after a large number of operations. Data errors can be checked and corrected using ECC (i.e., error correction code) techniques. With the rapid increase of the storage density of the flash memory, the reliability of the flash memory is reduced and the service life is shortened. Unreliable data storage in flash memory increases the error correction difficulty of ECC and may even lose valuable data. Further, FTL (flash translation layer) algorithms in memory controllers may be employed to refresh flash memory over time to improve data reliability. The data refresh process includes copying data from the physical block and reprogramming the physical block. However, when sequential data refreshing is performed on multiple physical blocks of a flash memory, the read and program operations of the data refreshing themselves may result in the loss of data from a portion of the physical blocks. Accordingly, it is desirable to further improve FTL algorithms of flash memories to increase the reliability of flash memories. Disclosure of Invention In view of the foregoing, an object of the present invention is to provide a data refreshing method and a controller for a flash memory, in which a physical block of the flash memory is divided into a plurality of sub-blocks, and a plurality of logical pages of the physical block are partitioned and moved during the data refreshing process, so as to improve the data reliability of the flash memory during the data refreshing process. According to one aspect of the invention, a data refreshing method for a flash memory is provided, comprising dividing a physical block of the flash memory into a plurality of sub-blocks through a reliability test, obtaining a reliability impact type of the physical block according to a read retry operation, obtaining a first reliability level of the plurality of sub-blocks of the physical block according to the reliability impact type of the physical block, obtaining a second reliability level of different types of logical pages of the physical block according to the reliability impact type of the physical block, sorting the plurality of logical pages of the physical block according to the first reliability level and the second reliability level, and moving the plurality of logical pages of the physical block according to the sorting. Preferably, the reliability test includes at least one of performing a program/erase cycle operation on the physical block, performing a data retention test in a high temperature environment, and performing a read disturb test in a normal temperature environment. Preferably, the reliability test obtains threshold voltage distributions and/or bit error rate distributions of a plurality of physical pages in the physical block. Preferably, the physical block is divided into a plurality of sub-blocks having different reliability levels according to a threshold voltage distribution and/or an error rate distribution. Preferably, during the use of the flash memory, the reliability test is performed multiple times to dynamically adjust the sub-block area and the number of sub-blocks in the physical block. Preferably, the read retry operation includes selecting a new set of read threshold voltages according to a retry table, and performing a read operation with the new set of read threshold voltages to identify a state of charge in the memo