CN-116936362-B - Method for manufacturing semiconductor device and semiconductor device

CN116936362BCN 116936362 BCN116936362 BCN 116936362BCN-116936362-B

Abstract

The application provides a manufacturing method of a semiconductor device and the semiconductor device, the method comprises the steps of firstly providing a substrate comprising a substrate, a bottom electrode layer, a storage material layer, a first dielectric layer and a top electrode layer, wherein the substrate, the bottom electrode layer, the storage material layer and the first dielectric layer are sequentially laminated, the first dielectric layer comprises a first opening, the first opening exposes part of the storage material layer, and the top electrode layer is positioned in the first opening; then, removing part of the top electrode layer along a first direction to form a plurality of prepared top electrodes arranged at intervals, then removing part of the prepared top electrodes along a second direction to form a plurality of top electrodes at intervals, wherein the second direction is perpendicular to the first direction, and finally, etching the storage material layer by taking the top electrode as a mask to expose part of the bottom electrode layer. By changing the removal area, the manufacture of a smaller top electrode is realized, and the size of the semiconductor device is ensured to meet the development requirement.

Inventors

YU ZHIMENG
HE SHIKUN

Assignees

中电海康集团有限公司

Dates

Publication Date: 20260512
Application Date: 20220407

Claims (10)

1. A method of fabricating a semiconductor device, comprising: Providing a substrate, wherein the substrate, the bottom electrode layer, the storage material layer and the first dielectric layer are sequentially laminated, the first dielectric layer comprises a first opening, part of the storage material layer is exposed through the first opening, and the top electrode layer is positioned in the first opening; removing a part of the top electrode layer along a first direction, wherein the rest of the top electrode layer forms a plurality of prepared top electrodes which are arranged at intervals, and the first direction is perpendicular to the thickness direction of the substrate; removing portions of the preliminary top electrodes along a second direction, such that each of the preliminary top electrodes forms a plurality of spaced top electrodes, the second direction being perpendicular to a direction of the substrate thickness, the second direction being perpendicular to the first direction; And etching the storage material layer by taking the top electrode as a mask, so that part of the bottom electrode layer is exposed, and the rest of the storage material layer forms a storage layer.
2. The method of claim 1, wherein after etching the memory material layer with the top electrode as a mask, the method further comprises: Depositing a second preliminary dielectric layer on the exposed surface of the top electrode and on the sides of the storage layer; Etching the bottom electrode layer and the second preparation medium layer so that part of the substrate is exposed, the top electrode and the storage layer are not exposed, the rest of the second preparation medium layer forms a second medium layer, and the rest of the bottom electrode layer forms a bottom electrode; forming a third dielectric layer on the exposed surface of the second dielectric layer and on the side surface of the bottom electrode; Removing part of the second dielectric layer and part of the third dielectric layer, wherein the rest of the second dielectric layer forms a second dielectric part, and the rest of the third dielectric layer forms a third dielectric part; and forming a first metal wire on the second dielectric part and the third dielectric part, wherein the first metal wire is in contact with the top electrode.
3. The method of claim 2, wherein etching the bottom electrode layer and the second preliminary dielectric layer comprises: The bottom electrode layer and the second preliminary dielectric layer are etched using a self-aligned process.
4. The method of claim 1, wherein providing a substrate comprises: Providing a substrate; sequentially depositing the bottom electrode layer, the storage material layer and a first preparation medium layer on the substrate; etching the first preparation medium layer to form the first opening, and forming the first medium layer by the rest of the first preparation medium layer; and filling electrode materials into the first opening to form the top electrode layer.
5. The method of claim 4, wherein providing a substrate comprises: Providing a substrate; depositing a fourth dielectric layer on the substrate; etching the fourth dielectric layer to expose part of the substrate to form a second opening, wherein the rest of the fourth dielectric layer forms a fourth dielectric part; filling electrode materials into the second opening to form the bottom electrode layer; Sequentially depositing the storage material layer and the first preparation medium layer on the exposed surfaces of the fourth medium part and the bottom electrode layer; etching the first preparation medium layer to form the first opening, and forming the first medium layer by the rest of the first preparation medium layer; and filling electrode materials into the first opening to form the top electrode layer.
6. The method of claim 4, wherein providing a substrate comprises: providing a preliminary substrate, the preliminary substrate comprising a plurality of third openings; And filling a metal material into the third opening to obtain a second metal wire, and forming the substrate.
7. The method of any of claims 1-6, wherein the material of the first dielectric layer comprises at least one of SiN, siO 2 , and SiON.
8. The method of claim 2, wherein etching the bottom electrode layer and the second preliminary dielectric layer comprises: And etching the bottom electrode layer and the second preparation medium layer, and cleaning the side surface of the bottom electrode layer and the exposed surface of the second preparation medium layer.
9. The method of claim 1, wherein removing portions of the top electrode layer along a first direction comprises: removing a portion of the top electrode layer along the first direction by a photolithography and etching process; removing a portion of the preliminary top electrode along a second direction, comprising: and removing part of the prepared top electrode along the second direction through photoetching and etching processes.
10. A semiconductor device manufactured by the method according to any one of claims 1 to 9.

Description

Method for manufacturing semiconductor device and semiconductor device Technical Field The application relates to the field of semiconductors, in particular to a manufacturing method of a semiconductor device and the semiconductor device. Background The memory structure of the current memory is that the memory cells are connected with two layers of metal wires through upper and lower electrodes, and along with the increasing requirement of future products on low writing current, the size of the memory cells is necessarily trend to be reduced. The current MRAM (Magnetic Random Access Memory ) size is about 70nm, and the existing technology can still meet the requirements. However, as the memory cell size continues to shrink, the associated processes are limited, such as photolithography and etch dimensional accuracy, nested alignment accuracy, and metal material fill issues with smaller critical dimensions (CD, critical Dimension), and therefore a fabrication process is needed to ensure that the memory cell size meets the development requirements. The above information disclosed in the background section is only for enhancement of understanding of the background art from the technology described herein and, therefore, may contain some information that does not form the prior art that is already known in the country to a person of ordinary skill in the art. Disclosure of Invention The application provides a manufacturing method of a semiconductor device and the semiconductor device, which are used for solving the problem that the size of a memory cell in the prior art cannot meet the development requirement due to the limitation of a manufacturing process. According to one aspect of the application, a manufacturing method of a semiconductor device is provided, the manufacturing method comprises the steps of providing a substrate, wherein the substrate comprises a substrate, a bottom electrode layer, a storage material layer, a first dielectric layer and a top electrode layer, the substrate, the bottom electrode layer, the storage material layer and the first dielectric layer are sequentially stacked, the first dielectric layer comprises a first opening, the first opening exposes part of the storage material layer, the top electrode layer is located in the first opening, part of the top electrode layer is removed along a first direction, a plurality of spare top electrodes which are arranged at intervals are formed on the rest of the top electrode layer, the first direction is perpendicular to the thickness direction of the substrate, part of the spare top electrodes is removed along a second direction, each spare top electrode forms a plurality of top electrodes which are arranged at intervals, the second direction is perpendicular to the thickness direction of the substrate, the top electrode is used as the top electrode, the rest of the storage material layer is etched, and the storage material layer is exposed. Optionally, after etching the storage material layer by taking the top electrode as a mask, the method further comprises depositing a second preparation medium layer on the exposed surface of the top electrode and the side surface of the storage layer, etching the bottom electrode layer and the second preparation medium layer so that part of the substrate is exposed and the top electrode and the storage layer are not exposed, forming a second medium layer by the rest of the second preparation medium layer, forming a third medium layer on the exposed surface of the second medium layer and the side surface of the bottom electrode, removing part of the second medium layer and part of the third medium layer, forming a second medium part by the rest of the second medium layer, forming a third medium part by the rest of the third medium layer, forming a first metal wire on the second medium part and the third medium part, and contacting the first metal wire with the top electrode. Optionally, etching the bottom electrode layer and the second preliminary dielectric layer includes etching the bottom electrode layer and the second preliminary dielectric layer using a self-aligned process. Optionally, providing a substrate, wherein the substrate comprises a substrate, sequentially depositing the bottom electrode layer, the storage material layer and a first preparation medium layer on the substrate, etching the first preparation medium layer to form a first opening, forming the first medium layer on the rest of the first preparation medium layer, and filling electrode materials into the first opening to form the top electrode layer. Optionally, providing a substrate, depositing a fourth dielectric layer on the substrate, etching the fourth dielectric layer to expose part of the substrate to form a second opening, forming a fourth dielectric part by the rest of the fourth dielectric layer, filling electrode materials into the second opening to form a bottom electrode layer, sequentially depositing the storage