CN-116936633-B - Super-junction MOSFET and manufacturing method thereof

CN116936633BCN 116936633 BCN116936633 BCN 116936633BCN-116936633-B

Abstract

The invention provides a super-junction MOSFET and a manufacturing method thereof, wherein the super-junction MOSFET comprises a substrate, a buffer area, a first conductive type column, a second conductive type column, a body area, a source area, a body contact area, a grid structure, a source electrode and a drain electrode, wherein the buffer area is stacked above the substrate; the first conductive type column and the second conductive type column are parallelly adjacent to the upper surface of the buffer zone, the body region is stacked on the second conductive type column, the source region is adjacent to the body contact region and is located on the upper surface layer of the body region, the grid structure comprises a grid dielectric layer, a first grid and second grids located on two sides of the first grid, the source electrode covers the upper surface of the device, and the drain electrode covers the bottom surface of the substrate. According to the invention, through designing the grid structure, the first grid of the first conductivity type and the second grid at least comprising the doped region of the second conductivity type replace the grid, so that the Miller capacitance when the drain-source voltage is lower is reduced, the Miller capacitance when the drain-source voltage is higher is not changed, and the on-resistance of the device is unchanged.

Inventors

LI PING
MA RONGYAO

Assignees

华润微电子（重庆）有限公司

Dates

Publication Date: 20260508
Application Date: 20220330

Claims (10)

1. A super-junction MOSFET which comprises a semiconductor substrate, characterized by comprising the following steps: a first conductivity type substrate; A first conductivity type buffer region on an upper surface of the substrate; A first conductive type column disposed on an upper surface of the buffer region and extending in a direction away from the substrate, the first conductive type column including a first column region and a second column region stacked on the first column region; The second conductive type column is arranged on the upper surface of the buffer area and positioned on two sides of the first column area, the side wall of the second conductive type column is adjacent to the side wall of the first column area, and the upper surface of the second conductive type column is flush with the upper surface of the first column area; a second conductive type body region stacked on the second conductive type column, and an upper surface of the body region is flush with an upper surface of the second column region, and a sidewall of the body region is adjacent to a sidewall of the second column region; The adjacent first conductive type source region and second conductive type body contact region are positioned on the upper surface layer of the body region, and the source region and the body contact region are spaced from the first conductive type column by a preset distance; The gate structure is positioned on the upper surface of the first conductive type column and at least comprises a gate dielectric layer, a first gate and second gates positioned on two sides of the first gate, wherein the gate dielectric layer wraps the first gate and the second gate, the first gate is positioned above the first conductive type column, the second gate is positioned above the source region, the first conductive type column, the source region and the body region among the first conductive type column, the first gate at least comprises a second conductive type doping region, and the second gate is of a first conductive type; And the source electrode covers the exposed surfaces of the grid structure, the source region and the body contact region, and the drain electrode covers the bottom surface of the substrate.
2. The super junction MOSFET as defined in claim 1, wherein said second conductivity type doped region is electrically connected to one of said second gate or said source.
3. The super junction MOSFET of claim 1, wherein said second conductivity type doped region is contiguous with said second gate when said first gate is entirely said second conductivity type doped region.
4. The super junction MOSFET of claim 3, wherein said second conductivity type doped region further comprises a first concentration region and a second concentration region disposed on opposite sides of said first concentration region, and wherein the doping concentration of said second concentration region is lower than the doping concentration of said first concentration region.
5. The super junction MOSFET of claim 1, wherein a first insulating medium layer is further disposed between said first gate and said second gate to isolate said first gate from said second gate.
6. The super junction MOSFET of claim 1, further comprising a first conductivity type doped region in said first gate.
7. The super junction MOSFET of claim 6, wherein said first conductivity type doped region is located between said second gate and said second conductivity type doped region, and wherein two ends of said first conductivity type doped region are adjacent to said second gate and said second conductivity type doped region, respectively.
8. The super junction MOSFET of claim 6, wherein said second conductivity type doped region is located between said first conductivity type doped region and said second gate, and wherein said second conductivity type doped region is adjacent to said first conductivity type doped region and said second gate, respectively.
9. The super junction MOSFET as defined in claim 6, wherein a second isolation dielectric layer is further disposed between the second conductivity type doped region and the first conductivity type doped region to isolate the second conductivity type doped region from the first conductivity type doped region.
10. The manufacturing method of the super junction MOSFET is characterized by comprising the following steps of: providing a first conductive type substrate, and forming a first conductive type buffer area on the upper surface of the substrate; Forming a first conductive type first column region and second conductive type columns positioned on two sides of the first column region on the upper surface of the buffer region, wherein the side walls of the second conductive type columns are adjacent to the side walls of the first column region, and the upper surface of the first column region is flush with the upper surface of the second conductive type columns; Forming a first conductive type second column region on the upper surface of the first column region, wherein the first column region and the second column region form a first conductive type column, forming second conductive type body regions which are positioned on the upper surface of the second conductive type column and are adjacent to the side wall of the second column region on two sides of the second column region, and the upper surface of the body region is flush with the upper surface of the second column region; Forming adjacent first-conductivity-type source regions and second-conductivity-type body contact regions in an upper surface layer of the body region, wherein the source regions and the body contact regions are spaced from the first-conductivity-type columns by a preset distance; Forming a gate structure on the upper surface of the first conductive type column, wherein the gate structure comprises a gate dielectric layer, a first gate and second gates positioned on two sides of the first gate, the gate dielectric layer wraps the first gate and the second gate, the first gate is positioned above the first conductive type column, the second gate is positioned above the source region, the first conductive type column, the source region and the body region between the first conductive type column, the first gate at least comprises a second conductive type doping region, and the second gate is of a first conductive type; And forming a source electrode covering the exposed surfaces of the gate structure, the source region and the body contact region, and forming a drain electrode covering the bottom surface of the substrate on the bottom surface of the substrate.

Description

Super-junction MOSFET and manufacturing method thereof Technical Field The invention belongs to the technical field of semiconductors, and relates to a super junction MOSFET and a manufacturing method thereof. Background The specific on-resistance in a typical power MOSFET is related to breakdown voltage to the power of 2.5, so for a power MOSFET, a high breakdown voltage tends to be accompanied by an exponentially increasing specific on-resistance, such as a 316-fold increase in specific on-resistance of a typical power MOSFET when the breakdown voltage increases from 50V to 500V. The super-junction MOSFET has the advantages that the relation between the specific on-resistance and the breakdown voltage to the power of 2.5 is changed to the power of 1.3, so that compared with the common power MOSFET, the super-junction MOSFET can greatly reduce the chip area under the same on-resistance, and further reduce the chip cost. The reduction of the chip area is also beneficial to reducing the parasitic capacitance of the device. For power MOSFETs, low parasitic capacitance, particularly low miller capacitance, is advantageous to reduce the time required for switching the device, thereby reducing switching losses and increasing efficiency. In addition, the switching time of the superjunction MOSFET can also be reduced in a manner that reduces the miller capacitance. At present, the miller capacitance of a full-voltage section in the super-junction MOSFET is generally reduced by adopting a split gate mode, but the miller capacitance of the full-voltage section is reduced by adopting the split gate mode, and meanwhile, the miller capacitance is extremely low when the voltage is large, so that the excessive dV/dt is easy to occur, the problems of current overshoot, RLC oscillation, electromagnetic interference (Electromagnetic Interference, EMI for short) and the like in an application loop are caused, and a part of channel electron accumulation layers are sacrificed by adopting the split gate mode, so that the on-resistance of a device is increased to a certain extent. In order to realize split gate in technology, a relatively complex technological process is required, and the manufacturing cost of the device is further increased. There are also ways to reduce the miller capacitance of the superjunction MOSFET by reducing the doping concentration of the JFET region, but reducing the doping concentration of the JFET causes an increase in the on-resistance of the device, requiring a larger chip area to achieve the same on-resistance, resulting in a larger parasitic capacitance, and thus reducing the switching speed of the device. Furthermore, lowering the doping concentration of the JFET region can only lower the miller capacitance at lower voltages without affecting the miller capacitance at higher voltages. Therefore, there is a need for a superjunction power MOSFET that can greatly optimize the miller capacitance without increasing the on-resistance of the device and the process difficulty. Disclosure of Invention In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a super-junction MOSFET and a method for manufacturing the same, which are used for solving the problems of increasing on-resistance and increasing process difficulty caused by reducing miller capacitance of the super-junction MOSFET in the prior art. To achieve the above and other related objects, the present invention provides a superjunction MOSFET including: a first conductivity type substrate; A first conductivity type buffer region on an upper surface of the substrate; A first conductive type column disposed on an upper surface of the buffer region and extending in a direction away from the substrate, the first conductive type column including a first column region and a second column region stacked on the first column region; The second conductive type column is arranged on the upper surface of the buffer area and positioned on two sides of the first column area, the side wall of the second conductive type column is adjacent to the side wall of the first column area, and the upper surface of the second conductive type column is flush with the upper surface of the first column area; a second conductive type body region stacked on the second conductive type column, and an upper surface of the body region is flush with an upper surface of the second column region, and a sidewall of the body region is adjacent to a sidewall of the second column region; The adjacent first conductive type source region and second conductive type body contact region are positioned on the upper surface layer of the body region, and the source region and the body contact region are spaced from the first conductive type column by a preset distance; The gate structure is positioned on the upper surface of the first conductive type column and at least comprises a gate dielectric layer, a first gate and second gates positi