CN-117037666-B - Shift register and driving method thereof, grid driving circuit and display device

CN117037666BCN 117037666 BCN117037666 BCN 117037666BCN-117037666-B

Abstract

The application provides a shift register, a driving method thereof, a grid driving circuit and a display device. The signal potential of the first node is maintained by the signal feedback circuit, so that a capacitive structure is omitted, and the problem that the voltage rising time of the pull-up node is long due to insufficient driving force in a capacitive coupling mode is solved.

Inventors

LIU WEIXING
PENG JINTAO
WANG XINXING
ZHANG CHUNFANG

Assignees

京东方科技集团股份有限公司
北京京东方技术开发有限公司

Dates

Publication Date: 20260508
Application Date: 20230822

Claims (10)

1. A shift register, comprising: A first input circuit electrically coupled to a first input signal terminal and a first voltage terminal and configured to receive a first signal provided by the first voltage terminal under control of a first input signal provided by the first input signal terminal; A potential control circuit electrically coupled to the first input circuit, the first node, and the second voltage terminal, and configured to supply a second signal supplied from the second voltage terminal to the first node under control of the first signal to control a signal potential of the first node to become a first level during a first period; A signal feedback circuit electrically coupled to the potential control circuit, the first node, and a third voltage terminal, configured to provide a third signal provided by the third voltage terminal to the potential control circuit under control of the second signal such that a signal potential of the first node is maintained at the first level for a second period; An output circuit electrically coupled to a fourth voltage terminal, an output signal terminal, and the first node, and configured to provide a fourth signal provided by the fourth voltage terminal to the output signal terminal under control of a signal of the first node during a third period; The signal feedback circuit comprises a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, wherein a first pole of the third transistor is connected to the first node, a second pole of the third transistor is connected to a twelfth voltage end, a third pole of the third transistor is connected to the second pole of the fourth transistor, a first pole of the fourth transistor is connected to the first node, a third pole of the fourth transistor is connected to the third voltage end, a first pole of the fifth transistor is connected to the potential control circuit, a second pole of the fifth transistor is connected to an eleventh voltage end, a third pole of the fifth transistor is connected to the second pole of the sixth transistor, a first pole of the sixth transistor is connected to the first node, and a third pole of the sixth transistor is connected to the clock control circuit.
2. The shift register of claim 1, wherein the shift register further comprises: A clock control circuit electrically coupled to the signal feedback circuit through the first node and electrically coupled to a clock signal terminal and a fifth voltage terminal, configured to output a fifth signal provided by the fifth voltage terminal under control of a first clock signal provided by the clock signal terminal and a signal of the first node in the third period; the output circuit is electrically coupled to the first node through the clock control circuit and is further configured to provide the fourth signal to the output signal terminal under control of the fifth signal.
3. The shift register of claim 2, wherein the shift register further comprises: A second input circuit electrically coupled to the clock control circuit through the signal feedback circuit and to a second input signal terminal and a sixth voltage terminal, configured to receive the sixth signal provided by the sixth voltage terminal under control of the second input signal provided by the second input signal terminal during a fourth period; The clock control circuit is further electrically coupled to a seventh voltage terminal and is further configured to provide a seventh signal provided by the seventh voltage terminal to the first node under control of the sixth signal to control the signal potential of the first node to become a second level.
4. The shift register of claim 3, wherein the clock control circuit is further electrically coupled to an eighth voltage terminal and a ninth voltage terminal, and further configured to output an eighth signal provided by the eighth voltage terminal and a ninth signal provided by the ninth voltage terminal under control of a second clock signal provided by the clock signal terminal and a signal of the first node during the fourth period; The output circuit is further electrically coupled to a tenth voltage terminal and is further configured to provide the tenth signal provided by the tenth voltage terminal to the output signal terminal under control of the eighth signal and the ninth signal.
5. The shift register of claim 3, wherein the signal feedback circuit is further electrically coupled to an eleventh voltage terminal and further configured to provide the eleventh signal provided by the eleventh voltage terminal to the first node under control of the first signal such that a signal potential of the first node is maintained at the first level.
6. The shift register of claim 3, wherein the signal feedback circuit is further electrically coupled to a twelfth voltage terminal and further configured to provide a twelfth signal provided by the twelfth voltage terminal to the clock control circuit under control of the seventh signal such that the signal potential of the first node is maintained at the second level.
7. The shift register of claim 3, wherein, The first input circuit comprises a first transistor, a first electrode of the first transistor is connected to the first input signal terminal, a second electrode of the first transistor is connected to the first voltage terminal, a third electrode of the first transistor is connected to the potential control circuit, and/or The potential control circuit comprises a second transistor with a first electrode connected to the first input circuit, a second electrode connected to the second voltage terminal, and a third electrode connected to the first node, and/or The clock control circuit comprises a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor, wherein the clock signal end comprises a first sub-clock signal end and a second sub-clock signal end, a first pole of the seventh transistor is connected to the first sub-clock signal end, a second pole of the seventh transistor is connected to a first pole of the eighth transistor, a third pole of the seventh transistor is connected to the output circuit, a fourth pole of the eighth transistor is electrically coupled with the signal feedback circuit through the first node, a third pole of the eighth transistor is connected to the seventh voltage end, a first pole of the ninth transistor is connected to the second sub-clock signal end, a second pole of the ninth transistor is connected to the eighth voltage end, a third pole of the tenth transistor is connected to the output circuit, a third pole of the tenth transistor is connected to the second pole of the eighth transistor, a third pole of the seventh transistor is connected to the tenth transistor, a third pole of the eighth transistor is connected to the tenth voltage end, a third pole of the ninth transistor is connected to the eighth voltage end, a fourth pole of the ninth transistor is connected to the eighth voltage end, a third pole of the eighth transistor is connected to the eighth voltage The second input circuit comprises a thirteenth transistor with a first electrode connected to the second input signal terminal, a second electrode connected to the sixth voltage terminal, a third electrode electrically coupled to the clock control circuit via the signal feedback circuit, and/or The output circuit comprises a fourteenth transistor and a fifteenth transistor, wherein a first pole of the fourteenth transistor is connected to a first pole of the fifteenth transistor, a second pole of the fourteenth transistor is connected to the fourth voltage terminal, a third pole of the fourteenth transistor is connected to the output signal terminal, the first pole of the fifteenth transistor is electrically coupled with the first node through the clock control circuit, a second pole of the fifteenth transistor is connected to the output signal terminal, and a third pole of the fifteenth transistor is connected to the tenth voltage terminal.
8. A gate drive circuit comprising a plurality of cascaded shift registers according to any one of claims 1-7.
9. A display device comprising the gate driving circuit according to claim 8.
10. A driving method of a shift register, applied to the shift register as claimed in any one of claims 1 to 7; The method comprises the following steps: receiving a first signal provided by the first voltage terminal under the control of a first input signal provided by the first input signal terminal in a first period; providing a second signal provided by the second voltage terminal to the first node under the control of the first signal so as to control the signal potential of the first node to become a first level; Providing a third signal provided by the third voltage terminal to the potential control circuit under control of the second signal during a second period, so that the signal potential of the first node is maintained at the first level during the second period; And in a third period, providing a fourth signal provided by the fourth voltage terminal to the output signal terminal under the control of the signal of the first node.

Description

Shift register and driving method thereof, grid driving circuit and display device Technical Field The present application relates to the field of display technologies, and in particular, to a shift register, a driving method thereof, a gate driving circuit and a display device. Background GOA (GATE DRIVE On Array) technology integrates a gate driving circuit On a display substrate, so that a gate driving chip is replaced, the structure of a display product is simplified, and the power consumption and cost of the display product are reduced. Such gate driving circuits generally employ a plurality of shift registers in cascade to realize the output of a plurality of gate signals. In the related art, a shift register maintains a voltage of a pull-up node through a capacitive coupling manner to realize output of a signal. However, the capacitive coupling method has a problem in that the voltage rise time of the pull-up node is long due to insufficient driving force. Disclosure of Invention In view of the above, the present application provides a shift register, a driving method thereof, a gate driving circuit and a display device, which solve or partially solve the above-mentioned problems. In view of the above object, a first aspect of the present application provides a shift register, comprising: A first input circuit electrically coupled to a first input signal terminal and a first voltage terminal and configured to receive a first signal provided by the first voltage terminal under control of a first input signal provided by the first input signal terminal; A potential control circuit electrically coupled to the first input circuit, the first node, and the second voltage terminal, and configured to supply a second signal supplied from the second voltage terminal to the first node under control of the first signal to control a signal potential of the first node to become a first level during a first period; A signal feedback circuit electrically coupled to the potential control circuit, the first node, and a third voltage terminal, configured to provide a third signal provided by the third voltage terminal to the potential control circuit under control of the second signal such that a signal potential of the first node is maintained at the first level for a second period; And an output circuit electrically coupled to the fourth voltage terminal, the output signal terminal and the first node, and configured to provide the fourth signal provided by the fourth voltage terminal to the output signal terminal under the control of the signal of the first node during a third period. In a second aspect of the present application, there is provided a gate drive circuit comprising a plurality of cascaded shift registers as described in the first aspect. In a third aspect of the present application, there is provided a display device comprising the gate driving circuit as described in the second aspect. In a fourth aspect, the present application provides a method for driving a shift register, which is applied to the shift register according to the first aspect, and the method includes: receiving a first signal provided by the first voltage terminal under the control of a first input signal provided by the first input signal terminal in a first period; providing a second signal provided by the second voltage terminal to the first node under the control of the first signal so as to control the signal potential of the first node to become a first level; Providing a third signal provided by the third voltage terminal to the potential control circuit under control of the second signal during a second period, so that the signal potential of the first node is maintained at the first level during the second period; And in a third period, providing a fourth signal provided by the fourth voltage terminal to the output signal terminal under the control of the signal of the first node. As can be seen from the above, the shift register, the driving method thereof, the gate driving circuit and the display device provided by the application realize the output of the gate signal through the first input circuit, the potential control circuit, the signal feedback circuit and the output circuit. The signal potential of the first node is maintained by the signal feedback circuit, so that a capacitive structure is omitted, and the problem that the voltage rising time of the pull-up node is long due to insufficient driving force in a capacitive coupling mode is solved. Drawings In order to more clearly illustrate the technical solutions of the present application or related art, the drawings that are required to be used in the description of the embodiments or related art will be briefly described below, and it is apparent that the drawings in the following description are only embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort to those of ordinary skill in the art.