CN-117094262-B - Analytic drawing method and device of FPGA chip model

CN117094262BCN 117094262 BCN117094262 BCN 117094262BCN-117094262-B

Abstract

The invention relates to an analysis drawing method and device of an FPGA chip model, the method comprises the steps of obtaining chip and circuit design information, analyzing chip structure data of an FPGA according to the chip and circuit design information, drawing according to the chip structure data to obtain a structure diagram of the FPGA, reversely analyzing network data and circuit layout data of the FPGA according to the chip and circuit design information, drawing on the structure diagram according to the network data and the circuit layout data to obtain an interconnection relation diagram of a layout diagram and a circuit layout of the FPGA, reversely analyzing circuit wiring data of the FPGA according to the chip and circuit design information, drawing on the layout diagram according to the circuit wiring data to obtain a wiring diagram of the FPGA. The analysis drawing method of the invention utilizes the resource analysis of different stages to complete the data analysis work, and the visual work of the chip structure, the circuit layout and the circuit wiring stage is completed through the drawing algorithm, thereby meeting the requirements of academic circles on the design of commercial FPGA architecture and the research of EDA algorithm.

Inventors

TIAN CONG
ZHANG XUESHI
YU BIN
DUAN ZHENHUA
Qu Nanjiang
LIU TING
WANG XIAOBING
ZHANG NAN
LU XU

Assignees

西安电子科技大学

Dates

Publication Date: 20260512
Application Date: 20220512

Claims (5)

1. The analytic drawing method of the FPGA chip model is characterized by comprising the following steps of: s1, acquiring chip and circuit design information, wherein the chip and circuit design information comprises a chip description file, a packaged netlist file, a circuit layout file and a circuit wiring file; S2, reversely analyzing to obtain chip structure data of the FPGA according to the chip and circuit design information, and drawing according to the chip structure data to obtain a structure diagram of the FPGA, wherein the S2 comprises the following steps: s21, reversely analyzing the chip structure data of the FPGA according to the chip description file, and converting the chip structure data into a grid array taking s_block as an element, wherein each element in the grid array corresponds to one piece of physical unit information, and the physical unit information comprises the name, the type, the position distribution, the pin type and the pin number of a physical unit; S22, traversing the grid array, analyzing the coordinates of each physical unit, drawing the boundaries of the physical units, and filling corresponding colors and text descriptions according to the types of the physical units to obtain a structure diagram of the FPGA; S3, reversely analyzing to obtain network data and circuit layout data of the FPGA according to the chip and circuit design information, and drawing on the structure diagram according to the network data and the circuit layout data to obtain an interconnection relation diagram of a layout diagram and a circuit layout of the FPGA, wherein the S3 comprises the following steps: S31, reversely analyzing the packed netlist file to obtain network data of the FPGA, and converting the network data into clb _ nets arrays taking an s_net structure body as an element, wherein each element in the clb _ nets array corresponds to one piece of network information, and the network information comprises the total network number, the physical unit position, the interconnection relation and the physical unit occupancy rate of the network; S32, reversely analyzing the circuit layout file to obtain circuit layout data of the FPGA, and converting the circuit layout data into a blocks array taking an s_block structure body as an element, wherein each element in the blocks array corresponds to one occupied physical unit information, and the occupied physical unit information comprises coordinates of occupied physical units, a network, an input node and an output node; S33, updating the occupation information of the physical units in the grid array according to the clb _ nets array and the blocks array; S34, marking all occupied physical units in the structural diagram according to the updated grid array and the clb _ nets array to obtain a layout diagram of the FPGA, and drawing a connection line from a SOURCE node corresponding to each network to a SINK node to obtain an interconnection relation diagram of the circuit layout; S4, reversely analyzing to obtain circuit wiring data of the FPGA according to the chip and the circuit design information, and drawing on the layout according to the circuit wiring data to obtain a wiring diagram of the FPGA, wherein the S4 comprises the following steps: S41, reversely analyzing the circuit wiring data of the FPGA according to the circuit wiring file, and converting the circuit wiring data into a trace_head array taking a route_node structure body as an element, wherein each element in the trace_head array corresponds to one piece of wiring network information, and the wiring network information comprises SOURCE nodes, SINK nodes, wiring resource nodes and wiring driving relations of a wiring network; s42, traversing the trace_head array, reading SOURCE nodes of each wiring network, and drawing wiring relations of the wiring network downwards from the SOURCE nodes to each wiring network on the layout according to a chained structure to obtain a wiring diagram of the FPGA.
2. The method according to claim 1, wherein in S22, if there are sub-units in the physical unit, all sub-units of the physical unit are traversed, coordinates of each sub-unit are resolved, and the sub-unit boundaries are drawn inside the physical unit.
3. An analytic drawing device of an FPGA chip model, characterized by implementing the method steps of any one of claims 1-2, comprising: The information acquisition module is used for acquiring the chip and circuit design information; the chip structure drawing module is used for reversely analyzing to obtain chip structure data of the FPGA according to the chip and circuit design information, and drawing according to the chip structure data to obtain a structure diagram of the FPGA; the layout drawing module is used for reversely analyzing the network data and the circuit layout data of the FPGA according to the chip and the circuit design information, drawing on the structure diagram according to the network data and the circuit layout data, and obtaining a layout diagram of the FPGA and an interconnection relation diagram of the circuit layout; And the wiring drawing module is used for reversely analyzing the circuit wiring data of the FPGA according to the chip and the circuit design information, and drawing on the layout diagram according to the circuit wiring data to obtain a wiring diagram of the FPGA.
4. An electronic device comprising a processor, a communication interface, a memory, and a communication bus, wherein, The processor, the communication interface, the memory is through the communication bus finishes the mutual communication; a memory for storing a computer program; A processor for implementing the method steps of any of claims 1-2 when executing a program stored on a memory.
5. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored therein a computer program which, when executed by a processor, implements the method steps of any of claims 1-2.

Description

Analytic drawing method and device of FPGA chip model Technical Field The invention belongs to the technical field of FPGA architecture design and electronic design automation, and particularly relates to an analytic drawing method and device of an FPGA chip model. Background The FPGA is widely applied to the civil digital fields such as mobile phones, communication equipment, automobiles, household appliances and the like and armament systems such as ships, missiles, fighters and the like at present, and the application range is still in a continuous expansion trend, so that the FPGA is a key facility for the national defense security. In recent years, with the development of semiconductor manufacturing processes, the number of logic units of an FPGA chip breaks through tens of millions, so that very large-scale complex circuit designs can be supported, and the most advanced devices now comprise billions of transistors and countless features. This exponential growth and feature evolution presents a profound problem for device functional architecture, presenting new challenges to the specialized EDA tools required for FPGA device design. Currently, ISE and Vivado etc. software is the first choice of designers, but the above software confidentiality is strong, different versions of EDA tools can only support a specified series of partial FPGA chips, and the use of EDA tools requires a regular payment of expensive fees. Chip modeling language has been widely used as an abstract description method for chips in academic EDA software such as academic VTR and Yosys + nextpnr. The chip modeling language is based on an extensible markup language and consists of a closed hierarchical modeling tag, and the modeling tag adds additional information to tag content through custom attributes. The structured modeling method utilizes XML language to construct a model standard, a group of modeling labels and modeling constraints, and has high expandability and flexibility. However, the chip modeling language is obscure and understandable, and the requirement on the professional knowledge of researchers for reading the chip model is extremely high, and the workload is extremely high. Moreover, current academic FPGA research is based on chip models described using structured modeling language, and abstract description approaches make commercial chip models too tedious to meet the needs of academic researchers. Disclosure of Invention In order to solve the problems in the prior art, the invention provides an analytic drawing method and device for an FPGA chip model. The technical problems to be solved by the invention are realized by the following technical scheme: the invention provides an analytic drawing method of an FPGA chip model, which comprises the following steps: S1, acquiring chip and circuit design information; S2, reversely analyzing to obtain chip structure data of the FPGA according to the chip and circuit design information, and drawing according to the chip structure data to obtain a structure diagram of the FPGA; S3, reversely analyzing to obtain network data and circuit layout data of the FPGA according to the chip and circuit design information, and drawing on the structure diagram according to the network data and the circuit layout data to obtain a layout diagram and an interconnection relation diagram of the circuit layout of the FPGA; and S4, reversely analyzing to obtain circuit wiring data of the FPGA according to the chip and the circuit design information, and drawing on the layout according to the circuit wiring data to obtain a wiring diagram of the FPGA. In one embodiment of the invention, the chip and circuit design information includes a chip description file, a packed netlist file, a circuit layout file, and a circuit routing file. In one embodiment of the present invention, the S2 includes: s21, reversely analyzing to obtain the chip structure data of the FPGA according to the chip description file, converting the chip structure data into a grid array taking s_block as an element, Each element in the grid array corresponds to one piece of physical unit information, and the physical unit information comprises the name, the type, the position distribution, the pin type and the pin number of the physical unit; And S22, traversing the grid array, analyzing the coordinates of each physical unit, drawing the boundaries of the physical units, and filling corresponding colors and text descriptions according to the types of the physical units to obtain the structure diagram of the FPGA. In one embodiment of the present invention, in the step S22, if a subunit exists in the physical unit, all subunits of the physical unit are traversed, coordinates of each subunit are resolved, and the subunit boundaries are drawn inside the physical unit. In one embodiment of the present invention, the S3 includes: S31, according to the packed netlist file, reversely analyzing to obtain the network data of the FPGA, co