CN-117153815-B - Semiconductor structure and forming method thereof

Abstract

The present disclosure relates to a semiconductor structure and a method of forming the same. The semiconductor structure comprises a substrate, a plurality of active columns, a plurality of word lines and a plurality of word lines, wherein the active columns are located in the substrate and are arranged in an array mode along a first direction and a second direction, the first direction and the second direction are parallel to the top surface of the substrate, the first direction is intersected with the second direction, the word lines are arranged at intervals along the first direction, each word line extends along the second direction and continuously covers part of side walls of the active columns arranged along the second direction, and any two adjacent word lines are at least partially staggered in the direction perpendicular to the top surface of the substrate. The semiconductor structure can reduce the capacitive coupling effect between two adjacent word lines, and has simple manufacturing process and easy realization and control.

Inventors

• XIAO DEYUAN
• JIANG YI
• SHAO GUANGSU
• SU XINGSONG
• QIU YUNSONG

Assignees

• 长鑫存储技术有限公司

Dates

Publication Date

20260512

Application Date

20220520

Claims (19)

1. 1. A semiconductor structure, comprising: A substrate; The active columns are positioned in the substrate, are arranged in an array along a first direction and a second direction, are parallel to the top surface of the substrate, intersect with the second direction and comprise a source electrode region, a channel region and a drain electrode region which are sequentially arranged along a direction perpendicular to the top surface of the substrate; The word lines are arranged at intervals along the first direction, each word line extends along the second direction and continuously covers part of the side walls of the active columns arranged along the second direction, and any two adjacent word lines are at least partially staggered along the direction perpendicular to the top surface of the substrate, and each word line continuously covers the channel regions of the active columns arranged along the second direction; A plurality of bit lines located within the substrate, the plurality of bit lines being arranged at intervals along the second direction, each of the bit lines extending along the first direction and being in contact electrical connection with the source regions of the plurality of active pillars arranged along the first direction; Wherein the source regions in any adjacent two of the active pillars in the first direction are different in size in a direction perpendicular to the top surface of the substrate.
2. 2. The semiconductor structure of claim 1, wherein a portion of the word lines of the plurality of word lines are first word lines and a portion of the word lines are second word lines; For a plurality of the active pillars arranged along the first direction, the first word line wraps around a portion of a sidewall of the active pillar of a first parity sequence, and the second word line wraps around a portion of a sidewall of the active pillar of a second parity sequence.
3. 3. The semiconductor structure of claim 2, wherein a top surface of the first word line is below a bottom surface of the second word line, or The top surface of the first word line is above the bottom surface of the second word line, and the top surface of the first word line is below the top surface of the second word line.
4. 4. The semiconductor structure of claim 2, wherein a top surface of the first word line is located below a bottom surface of the second word line, wherein a predetermined gap is provided between the top surface of the first word line and the bottom surface of the second word line, and wherein a width of the predetermined gap is 1/4 to 1/2 of a size of the first word line in a direction perpendicular to the top surface of the substrate.
5. 5. The semiconductor structure of claim 1, further comprising: an insulating layer covering the side wall of the source region; The grid dielectric layer covers the side wall of the channel region and the side wall of the drain region, and the word line is positioned on the surface of the grid dielectric layer on the channel region; and the isolation layer is positioned between the adjacent active columns and covers the surface of the insulation layer, the surface of the word line and the surface of the gate dielectric layer of the side wall of the drain region.
6. 6. The semiconductor structure of claim 1, wherein a plurality of said word lines are all equal in size in a direction perpendicular to a top surface of said substrate.
7. 7. The semiconductor structure of claim 1, wherein a portion of the word lines in the plurality of word lines are first word lines, a portion of the word lines are second word lines, and a portion of the word lines are third word lines; For a plurality of the active pillars arranged along the first direction, the first word line wraps a portion of a sidewall of the active pillar of the 3 n-th bit, the second word line wraps a portion of a sidewall of the active pillar of the 3n+1-th bit, and the third word line wraps a portion of a sidewall of the active pillar of the 3n+2-th bit, wherein n is an integer greater than or equal to 0.
8. 8. A method of forming a semiconductor structure, comprising: Providing a substrate; Forming a plurality of active columns in the substrate, wherein the active columns are arranged in an array along a first direction and a second direction, the first direction and the second direction are both directions parallel to the top surface of the substrate, the first direction is intersected with the second direction, and the active columns comprise a source electrode region, a channel region and a drain electrode region which are sequentially arranged along a direction perpendicular to the top surface of the substrate; forming a plurality of bit lines in the substrate, the bit lines being arranged at intervals along the second direction, each bit line extending along the first direction and being electrically connected to bottom contacts of a plurality of active pillars arranged along the first direction, and Forming a plurality of word lines, wherein the word lines are arranged at intervals along the first direction, each word line extends along the second direction and continuously covers part of side walls of a plurality of active columns arranged along the second direction, and any two adjacent word lines are at least partially staggered along the direction perpendicular to the top surface of the substrate, and each word line continuously covers the channel regions of a plurality of active columns arranged along the second direction; Wherein the source regions in any adjacent two of the active pillars in the first direction are different in size in a direction perpendicular to the top surface of the substrate.
9. 9. The method of claim 8, wherein forming the plurality of active pillars within the substrate comprises: Etching the substrate to form a plurality of first grooves, wherein the plurality of first grooves are arranged at intervals along the second direction, and each first groove extends along the first direction; forming a first filling layer filling the plurality of first trenches, and And etching the substrate to form a plurality of second grooves, wherein the second grooves are arranged at intervals along the first direction, and each second groove extends along the second direction.
10. 10. The method of forming a semiconductor structure of claim 8, wherein after forming the plurality of active pillars, before forming the plurality of word lines, further comprising: an insulating layer is formed covering the top and side surfaces of the plurality of active pillars.
11. 11. The method of claim 8, wherein the active pillars are silicon and the plurality of bit lines are formed using a silicon metallization process.
12. 12. The method of claim 10, wherein a portion of the word lines in the plurality of word lines are first word lines and a portion of the word lines are second word lines, wherein the first word lines cover a portion of sidewalls of the active pillars of a first parity sequence and the second word lines cover a portion of sidewalls of the active pillars of a second parity sequence for the plurality of active pillars arranged in the first direction.
13. 13. The method of forming a semiconductor structure of claim 12, wherein forming the plurality of word lines comprises: Forming an isolation layer which fills the second groove and covers the surface of the insulation layer; Etching part of the insulating layer to form a second groove between the active column and the isolating layer of the second parity sequence; forming a second word line in the second groove; Etching part of the insulating layer to form a first groove between the active column and the isolation layer of the first parity sequence, wherein the depth of the first groove is different from that of the second groove; And forming a first word line in the first groove, wherein the second word line is staggered with the first word line in the direction perpendicular to the top surface of the substrate.
14. 14. The method of forming a semiconductor structure of claim 13, wherein forming a second word line within the second recess comprises: forming an initial second word line filling the second groove; Etching back part of the initial second word line to form the second word line and a third groove above the second word line; and forming a second filling layer filling the third groove.
15. 15. The method of forming a semiconductor structure of claim 13, wherein a bottom surface of the first recess is above a bottom surface of the second recess and the bottom surface of the first recess is below a top surface of the second word line, or The bottom surface of the first groove is positioned above the top surface of the second word line.
16. 16. The method of forming a semiconductor structure of claim 13, wherein forming a first word line within the first recess comprises: forming an initial first word line filling the first groove; etching back part of the initial first word line to form the first word line and a fourth groove above the first word line; And forming a third filling layer filling the fourth groove.
17. 17. The method of forming a semiconductor structure of claim 12, wherein forming the plurality of word lines comprises: Forming an isolation layer which fills the second groove and covers the surface of the insulation layer; The insulating layer is etched and the insulating layer is etched, forming a second groove between the active pillars of the second parity sequence and the isolation layer, and a first groove between the active pillars of the first parity sequence and the isolation layer, the first groove and the second groove have different depths; And forming a second word line in the second groove and forming a first word line in the first groove, wherein the second word line and the first word line are staggered in the direction perpendicular to the top surface of the substrate.
18. 18. The method of forming a semiconductor structure of claim 17, wherein forming the second recess between the active pillars of the second parity sequence and the isolation layer, and the first recess between the active pillars of the first parity sequence and the isolation layer, comprises: etching the insulating layer between the active pillars and the isolation layer of the second parity sequence to form an initial second groove; etching the insulating layer between the active pillars and the isolation layer of the first parity sequence and the insulating layer at the bottom of the initial second groove to form the first groove and the second groove, respectively.
19. 19. The method of claim 18, wherein forming a first word line in the first recess and a second word line in the second recess comprises: Depositing a conductive material layer filling the first groove and the second groove; Etching back the conductive material layer in the second groove; And etching the second groove and the conductive material layer in the first groove again, wherein the conductive material layer remained in the second groove forms the second word line, and the conductive material layer remained in the first groove forms the first word line.

Description

Semiconductor structure and forming method thereof Technical Field The present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method for forming the same. Background Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor device commonly used in electronic devices such as computers, and is composed of a plurality of memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected with a word line, the source is electrically connected with a bit line, and the drain is electrically connected with a capacitor, and the word line voltage on the word line can control the on and off of the transistor, so that data information stored in the capacitor can be read or written into the capacitor through the bit line. However, in a semiconductor structure such as a dynamic random access memory, all word lines are located at the same level, and the coupling effect between adjacent word lines is strong due to the narrow spacing between adjacent word lines. When one word line is selected to be turned on, due to a strong coupling effect, the adjacent word line can be turned on instantaneously, and finally, problems such as capacitor leakage, even read-write failure and the like can be caused, so that the performance of the memory is seriously affected. Therefore, how to reduce the coupling effect between adjacent word lines, thereby improving the performance of the memory, is a technical problem to be solved. Disclosure of Invention The semiconductor structure and the forming method thereof provided by some embodiments of the present disclosure are used for reducing the coupling effect between adjacent word lines, thereby improving the performance of the memory and increasing the yield of the memory. According to some embodiments, the semiconductor structure comprises a substrate, a plurality of active columns located in the substrate, wherein the active columns are arranged in an array along a first direction and a second direction, the first direction and the second direction are both directions parallel to the top surface of the substrate and intersect with the second direction, a plurality of word lines are arranged at intervals along the first direction, each word line extends along the second direction and continuously covers part of side walls of the active columns arranged along the second direction, and any two adjacent word lines are at least partially staggered along the direction perpendicular to the top surface of the substrate. In some embodiments, a portion of the word lines in the plurality of word lines are first word lines and a portion of the word lines are second word lines, the first word lines cladding a portion of sidewalls of the active pillars of a first parity sequence for a plurality of the active pillars arranged along the first direction, the second word lines cladding a portion of sidewalls of the active pillars of a second parity sequence. In some embodiments, the top surface of the first word line is below the bottom surface of the second word line, or the top surface of the first word line is above the bottom surface of the second word line and the top surface of the first word line is below the top surface of the second word line. In some embodiments, the top surface of the first word line is located below the bottom surface of the second word line, a preset gap is formed between the top surface of the first word line and the bottom surface of the second word line, and the width of the preset gap is 1/4-1/2 of the size of the first word line in the direction perpendicular to the top surface of the substrate. In some embodiments, the active pillars comprise a source region, a channel region, and a drain region sequentially arranged in a direction perpendicular to the top surface of the substrate, each of the word lines continuously surrounds the channel region of a plurality of the active pillars arranged in the second direction, the semiconductor structure further comprises a plurality of bit lines within the substrate, the plurality of bit lines being spaced apart in the second direction, each of the bit lines extending in the first direction and being in contact electrical connection with the source regions of a plurality of the active pillars arranged in the first direction. In some embodiments, the semiconductor device further comprises an insulating layer, a gate dielectric layer, an isolation layer and a spacer layer, wherein the insulating layer covers the side wall of the source region, the gate dielectric layer covers the side wall of the channel region and the side wall of the drain region, the word line is located on the surface of the gate dielectric layer on the channel region, the isolation layer is located between adjacent active columns, and the isolation layer covers the surface of the insulating laye