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CN-117155377-B - Composite logic gate circuit, chip and electronic device comprising same

CN117155377BCN 117155377 BCN117155377 BCN 117155377BCN-117155377-B

Abstract

The composite logic gate circuit comprises a driving circuit and is provided with a signal output end and K signal input ends, wherein the first end of the driving circuit is connected to the signal output end of the composite logic gate circuit and is connected to a high-level power supply through a load circuit, the second end of the driving circuit is connected to a low-level power supply, the driving circuit comprises K first depletion type HEMT devices and L clamping devices, the K first depletion type HEMT devices are arranged into M and structures, the L clamping devices are arranged into M clamping units, each clamping unit corresponds to one clamping unit, M and L are positive integers, and K is an integer greater than or equal to 2. According to the embodiment of the application, the composite logic gate circuit is constructed by the depletion type field effect transistor based on the compound semiconductor substrate, so that the performance density and the functional density of the high-end radio frequency system of the compound mixed circuit can be improved, the cost is reduced, and the reliability is improved.

Inventors

  • LIU SHISHENG

Assignees

  • 深圳市晶准通信技术有限公司

Dates

Publication Date
20260508
Application Date
20220524

Claims (13)

  1. 1. A composite logic gate circuit comprising a drive circuit and having a signal output terminal and K signal input terminals, a first terminal of the drive circuit being connected to the signal output terminal of the composite logic gate circuit and to a high level power supply through a load circuit, a second terminal of the drive circuit being connected to a low level power supply, wherein the first terminal of the load circuit is connected to the first terminal of the drive circuit and the signal output terminal of the composite logic gate circuit, and a second terminal of the load circuit is connected to the high level power supply, wherein the drive circuit comprises K first depletion mode HEMT devices and L clamp devices, the K first depletion mode HEMT devices being arranged on a compound semiconductor substrate and in M and structures, the L clamp devices being arranged in M clamp units, wherein each and structure corresponds to one clamp unit, M and L being positive integers, K being integers greater than or equal to 2, wherein: Each and structure comprises one or more first depletion mode HEMT devices, wherein the 1 st to M th and structures respectively comprise K 1 、……、K M first depletion mode HEMT devices, K 1 、……、K M is the same or different positive integers, and the sum of K 1 、……、K M is equal to K; the grid electrodes of the K first depletion type HEMT devices are in one-to-one correspondence with the K signal input ends of the composite logic gate circuit, and the grid electrode of each of the K first depletion type HEMT devices is connected to a corresponding one of the K signal input ends; In an AND structure comprising a plurality of first depletion mode HEMT devices, the plurality of first depletion mode HEMT devices in the AND structure are connected in series, wherein the drain electrode of a first depletion mode HEMT device in the AND structure is connected to a first end of the driving circuit, the source electrode of a last first depletion mode HEMT device in the AND structure is connected to the head end of a corresponding one of the clamping units, the drain electrode of each other first depletion mode HEMT device in the AND structure is connected to the source electrode of a previous first depletion mode HEMT device in the AND structure, and the source electrode of each other first depletion mode HEMT device in the AND structure is connected to the drain electrode of a subsequent first depletion mode HEMT device in the AND structure; Each clamping unit comprises one or more clamping devices, each clamping device is provided with a first end and a second end, wherein the 1 st to M th clamping units respectively comprise L 1 、……、L M clamping devices, L 1 、……、L M is the same or different positive integers, and the sum of L 1 、……、L M is equal to L; In a clamping unit including a plurality of clamping devices, the plurality of clamping devices in the clamping unit are connected in series, wherein a first end of a first clamping device in the clamping unit serves as a head end of the clamping unit, a second end of a last clamping device in the clamping unit serves as a tail end of the clamping unit, a first end of each other clamping device in the clamping unit is connected to a second end of a previous clamping device in the clamping unit, a second end of each other clamping device in the clamping unit is connected to a first end of a subsequent clamping device in the clamping unit, wherein the tail end of the clamping unit is connected to a second end of the driving circuit, and in a clamping unit including one clamping device, the first end of the clamping device serves as a head end of the clamping unit, and the second end of the clamping device serves as a tail end of the clamping unit and is connected to a second end of the driving circuit.
  2. 2. The composite logic gate of claim 1, wherein the clamp device is a compound-based diode with an anode of the diode as a first terminal of the clamp device and a cathode of the diode as a second terminal of the clamp device.
  3. 3. The composite logic gate circuit of claim 1, wherein the clamp device is a second depletion mode HEMT device, wherein a gate of the second depletion mode HEMT device serves as a first end of the clamp device, and wherein: The drain electrode of the second depletion type HEMT device is used as the second end of the clamping device, or The source electrode of the second depletion type HEMT device is used as the second end of the clamping device, or And the drain electrode and the source electrode of the second depletion type HEMT device are in short circuit together to serve as a second end of the clamping device.
  4. 4. The composite logic gate circuit of claim 1, wherein: The high level power supply is positive voltage power supply, and the low level power supply is ground, or The high level power supply is ground, the low level power supply is negative pressure power supply, or The high-level power supply is a positive-voltage power supply, and the low-level power supply is a negative-voltage power supply.
  5. 5. The composite logic gate of claim 1, wherein the K first depletion mode HEMT devices are formed on the same compound substrate.
  6. 6. The composite logic gate of claim 1 or 5, wherein the compound substrate comprises at least one of GaAs, gaN, and InP.
  7. 7. The composite logic gate circuit of claim 1, further comprising K level shifter circuits in one-to-one correspondence with the K first depletion mode HEMT devices, wherein each level shifter circuit is connected between a gate of a corresponding first depletion mode HEMT device and a signal input terminal corresponding to the first depletion mode HEMT device for converting a signal input to the signal input terminal into an input logic signal suitable for the first depletion mode HEMT device.
  8. 8. The composite logic gate circuit of claim 7, wherein an i-th level shifter circuit of the K level shifter circuits comprises N i level shifting elements, a first resistor R 1i , a second resistor R 2i , and a third resistor R 3i , wherein i = 1, wherein K, N 1 、……、N K are the same or different positive integers, wherein: The N i level shifting elements and the first resistor R 1i are connected in series to form a series circuit, wherein the first resistor R 1i is connected between the head end, the tail end or any two level shifting elements of the N i level shifting elements of the series circuit, each of the N i level shifting elements and the first resistor R 1i is used as a series unit of the series circuit to form N i +1 series units, the first end of a first series unit of the N i +1 series units is connected to a corresponding signal input end of the K signal input ends, the second end of a last series unit of the N i +1 series units is connected to the first end of the second resistor R 2i and the first end of the third resistor R 3i , the first end of each other series unit of the N i +1 series units is connected to the second end of the previous series unit, and the second end of each other series unit of the N i +1 series units is connected to the first end of the subsequent series unit; The second end of the third resistor R 3i is connected with a reference level signal, and the second end of the second resistor R 2i is connected to the gate of the corresponding first depletion mode HEMT device, so as to input the converted input logic signal to the first depletion mode HEMT device.
  9. 9. The composite logic gate circuit of claim 8, wherein the level shifting element is a compound-based diode having a positive pole as a first end of the series cell and a negative pole as a second end of the series cell.
  10. 10. The composite logic gate circuit of claim 8, wherein the level shifting element is a third depletion mode HEMT device, wherein a gate of the third depletion mode HEMT device is the first end of the series cell, and wherein: The drain electrode of the third depletion type HEMT device is used as the second end of the series unit, or The source electrode of the third depletion type HEMT device is used as the second end of the series unit, or And the drain electrode and the source electrode of the third depletion type HEMT device are in short circuit connection to serve as a second end of the series unit.
  11. 11. The composite logic gate circuit of claim 1, wherein the load circuit comprises a fourth depletion mode HEMT device and a clamp choke resistor, wherein a drain of the fourth depletion mode HEMT device is connected to the second end of the load circuit, a source of the fourth depletion mode HEMT device is connected to the first end of the clamp choke resistor, and a gate of the fourth depletion mode HEMT device and the second end of the clamp choke resistor are connected to the first end of the load circuit.
  12. 12. A chip comprising a composite logic gate as claimed in any one of claims 1 to 11.
  13. 13. An electronic device comprising the chip of claim 12.

Description

Composite logic gate circuit, chip and electronic device comprising same Technical Field The application belongs to the technical field of semiconductors, and particularly relates to a composite logic gate circuit, a chip comprising the composite logic gate circuit and an electronic device. Background The existing high-performance radio frequency or microwave millimeter wave devices or circuits mostly adopt compound devices as cores. For example, the high-performance switch in the mobile communication device adopts GAAS PHEMT technology, the high-performance power amplifier adopts GAAS PHEMT technology, the power amplifier and the switch of the 5G base station adopt GaN HEMT, the high-end high-frequency instrument adopts InP pHEMT technology device or chip as core device, and the high-performance radar system also adopts GaAs depletion pHEMT or GaN depletion HEMT as core radio frequency device. With the development of civil high-frequency mobile communication, internet of vehicles and large satellite constellations, the radio frequency system is developed towards higher performance density, higher functional integration and more flexibility. However, in the prior art, for driving control of a compound device or circuit (for example, controlling the gate voltage of a field-effect transistor in a switching circuit or the gate voltage of a field-effect transistor in an amplifier), an additional Si-based or GeSi BiCMOS chip or circuit is generally required, which requires a high cost packaging technology and a more complex process flow. In addition, since the material characteristics of the compound and Si or GeSi are different, for example, the thermal expansion coefficient, the trend of the device with temperature, and the like are different, it is difficult to achieve improvement of the performance density and the functional density at the same time. The high cost, system complexity, etc. associated with control of the rf circuitry based on the compound device is becoming a short board affecting its application development. Therefore, finding an integrated driving or controlling function based on high-performance rf or microwave/millimeter wave compound devices is beneficial to solving the above problems. Disclosure of Invention The embodiment of the application provides a composite logic gate circuit, a chip comprising the composite logic gate circuit and an electronic device. According to an aspect, an embodiment of the present application provides a composite logic gate circuit, including a driving circuit, and having a signal output terminal and K signal input terminals, a first terminal of the driving circuit being connected to the signal output terminal of the composite logic gate circuit and connected to a high level power supply through a load circuit, a second terminal of the driving circuit being connected to a low level power supply, wherein the first terminal of the load circuit is connected to the first terminal of the driving circuit and the signal output terminal of the composite logic gate circuit, and a second terminal of the load circuit is connected to the high level power supply, wherein the driving circuit includes K first depletion mode HEMT devices arranged on a compound semiconductor substrate and arranged in M and structures, the L clamp devices being arranged in M clamp units, wherein each and structure corresponds to one clamp unit, M and L are positive integers, and K is an integer greater than or equal to 2, and wherein the driving circuit includes K first depletion mode HEMT devices arranged on a compound semiconductor substrate and L clamp devices. Each and structure comprises one or more first depletion mode HEMT devices, wherein the 1 st to M th and structures respectively comprise K 1、……、KM first depletion mode HEMT devices, K 1、……、KM is the same or different positive integers, and the sum of K 1、……、KM is equal to K; the grid electrodes of the K first depletion type HEMT devices are in one-to-one correspondence with the K signal input ends of the composite logic gate circuit, and the grid electrode of each of the K first depletion type HEMT devices is connected to a corresponding one of the K signal input ends; In an AND structure comprising a plurality of first depletion mode HEMT devices, the plurality of first depletion mode HEMT devices in the AND structure are connected in series, wherein the drain electrode of a first depletion mode HEMT device in the AND structure is connected to a first end of the driving circuit, the source electrode of a last first depletion mode HEMT device in the AND structure is connected to the head end of a corresponding one of the clamping units, the drain electrode of each other first depletion mode HEMT device in the AND structure is connected to the source electrode of a previous first depletion mode HEMT device in the AND structure, and the source electrode of each other first depletion mode HEMT device in the AND structure is connected t