CN-117176170-B - Sigma-delta modulator circuit

Abstract

Embodiments of the present disclosure provide a Sigma-delta modulator circuit. The modulator circuit comprises an integrating module, an adder module, a comparator and a feedback digital-to-analog conversion module, wherein the integrating module performs integrating operation on a difference value between an input signal and the output of the feedback digital-to-analog conversion module to obtain an integrator output result, the adder module performs summation operation on the input signal and the integrated output result, the output of the adder module is connected to the comparator, the output of the comparator is fed back to the integrating module through the feedback digital-to-analog conversion module, the output of the comparator is an output signal, the modulator circuit is controlled by a first clock signal, a second clock signal and a third clock signal, the first clock signal and the second clock signal are two non-overlapping clock signals, the third clock signal arrives earlier than the second clock signal, and under the control of the three clock signals, the Sigma-Delta modulator circuit with high common-mode input capacity and low input offset voltage is realized.

Inventors

• BAI WEI
• YU XIANG
• XIE CHENGYI

Assignees

• 圣邦微电子（北京）股份有限公司

Dates

Publication Date

20260512

Application Date

20220527

Claims (10)

1. 1. The Sigma-delta modulator circuit is characterized by comprising an integrating module, an adder module, a comparator and a feedback digital-to-analog conversion module, wherein the integrating module performs integrating operation on a difference value of an input signal and an output of the feedback digital-to-analog conversion module to obtain an integrator output result, the adder module performs summation operation on the input signal and the integration output result, the output of the adder module is connected to the comparator, the output of the comparator is fed back to the integrating module through the feedback digital-to-analog conversion module, the output of the comparator is an output signal, the input signal is a high-common-mode input signal, a sampling capacitor in a first stage integrating unit in the integrating module is a high-voltage capacitor, a feedback capacitor in the feedback digital-to-analog conversion module is a high-voltage capacitor, and the adder module receives the input signal through the high-voltage capacitor; The modulator circuit is controlled by three clock signals of a first clock signal, a second clock signal and a third clock signal, the periods of the three clock signals are the same, the first clock signal and the second clock signal are two-phase non-overlapping clock signals, the third clock signal arrives earlier than the second clock signal, the integration module and the adder module sample and store offset voltage samples of a transconductance operational amplifier of the first-stage integration unit when the first clock signal is in a high level, the adder module performs summation operation and comparison operation when the third clock signal is in a high level, the comparator performs comparison operation and latches the comparison operation result, the integration module performs integration operation when the second clock signal is in a high level, the offset voltage is eliminated, and the output of the comparator is fed back to the integration module for subtraction operation.
2. 2. The Sigma-delta modulator circuit of claim 1, wherein if said modulator circuit is of a one-bit quantized, second-order full feed forward construction, said integrating module comprises a first stage integrating unit and a second stage integrating unit, said first stage integrating unit being connected in series with said second stage integrating unit, said first stage integrating unit integrating the difference between said input signal and the output of the feedback digital-to-analog conversion module, said second stage integrating unit integrating the output of said first stage integrating unit.
3. 3. The Sigma-delta modulator circuit of claim 2, wherein said input signal comprises a first input signal and a second input signal, wherein said first stage integrator unit comprises four first switches, four second switches, two first sampling capacitors, a first transconductance operational amplifier, two first integrating capacitors, wherein two ends of a first switch are connected to one ends of said first input signal and first sampling capacitor, two ends of a second first switch are connected to one ends of said second input signal and second first sampling capacitor, respectively, a third first switch, a fourth first switch are connected in parallel to two ends of said first transconductance operational amplifier, respectively, the two ends of the first second switch are respectively connected with one end of the second input signal and one end of the first sampling capacitor, the two ends of the second switch are respectively connected with one end of the first input signal and one end of the second first sampling capacitor, the third second switch is connected with the first integrating capacitor in series and then connected with the first transconductance operational amplifier in parallel, the fourth second switch is connected with the second first integrating capacitor in series and then connected with the first transconductance operational amplifier in parallel, the other ends of the two first sampling capacitors are respectively connected with the first transconductance operational amplifier, the control signal of the first switch is the first clock signal, and the control signal of the second switch is the second clock signal.
4. 4. The Sigma-delta modulator circuit of claim 2, wherein said second stage integrator unit comprises four first switches, four second switches, two second sampling capacitors, a second transconductance operational amplifier, and two second integration capacitors, wherein one end of the first second switch is grounded, the other end of the first second switch is connected to one end of the first switch and one end of the first second sampling capacitor, one end of the second switch is grounded, the other end of the second switch is connected to one end of the second first switch and one end of the second sampling capacitor, the other end of the first switch is connected to the output end of said first stage integrator unit, the other end of the second first switch is connected with the output end of the first stage integration unit, one end of the third first switch is grounded, the other end of the third first switch is respectively connected with the other end of the first second sampling capacitor and one end of the third second switch, one end of the fourth first switch is grounded, the other end of the fourth first switch is respectively connected with the other end of the second sampling capacitor and one end of the fourth second switch, the other ends of the third second switch and the fourth second switch are respectively connected with the second transconductance operational amplifier, the two second integration capacitors are respectively connected in parallel with the two ends of the second transconductance operational amplifier, the control signals of the first switch are the first clock signals, and the control signals of the second switch are the second clock signals.
5. 5. The Sigma-delta modulator circuit of claim 4, wherein said adder module comprises eight first switches, eight third switches, a third transconductance operational amplifier, two first feedforward capacitors, two second feedforward capacitors, two third feedforward capacitors, two summing capacitors, wherein the two ends of the first switch are respectively connected to one end of said first input signal and the first feedforward capacitor, the two ends of the second first switch are respectively connected to one end of said first input signal and the second first feedforward capacitor, the two ends of the first third switch are respectively connected to one end of said second input signal and the first feedforward capacitor, the two ends of the second third switch are respectively connected to one end of said second input signal and the first feedforward capacitor, the first end of the third switch is grounded, the other end of the third switch is respectively connected to one end of the first second feedforward capacitor, the two ends of the second stage integrator unit are respectively connected to the other end of the second input signal and the first feedforward capacitor, the other end of the third switch is respectively connected to the second end of the third switch, the other end of the third switch is respectively connected to the second end of the third stage integrator unit, the second switch is respectively connected to the other end of the third switch, the third switch is respectively connected to the second end of the third input signal and the second feedforward capacitor, the other end of the fourth first switch is connected with the output end of the second stage integration unit, one end of the fifth first switch is grounded, the other end of the fifth first switch is respectively connected with the other end of the first feedforward capacitor, the other end of the first second feedforward capacitor, the other end of the first third feedforward capacitor and one end of the seventh third switch, one end of the sixth first switch is grounded, the other end of the sixth first switch is respectively connected with the other end of the second first feedforward capacitor, the other end of the second feedforward capacitor, the other end of the second third feedforward capacitor and one end of the eighth third switch, the other ends of the seventh third switch and the eighth third switch are respectively connected with the third operational amplifier, the seventh first switch is connected with the first summing capacitor in parallel and then connected with the two ends of the third transconductance operational amplifier in parallel, the eighth first switch is connected with the second summing capacitor in parallel and then connected with the two ends of the third transconductance operational amplifier, and the third clock signal is the third clock signal.
6. 6. The Sigma-delta modulator circuit of claim 3, wherein said feedback digital-to-analog conversion module comprises a digital-to-analog conversion unit, two first switches, two second switches, and two feedback capacitors, wherein one ends of the two second switches are respectively connected to one end of said digital-to-analog conversion unit, one end of the first switch is grounded, the other end of the first switch is respectively connected to the other end of the first second switch and one end of the first feedback capacitor, one end of the second first switch is grounded, the other end of the second first switch is respectively connected to the other end of the second switch and one end of the second feedback capacitor, the other end of said digital-to-analog conversion unit is connected to said comparator, the other end of the first feedback capacitor is connected to the first sampling capacitor, and the other end of the second feedback capacitor is connected to the second first sampling capacitor.
7. 7. The Sigma-delta modulator circuit of claim 2, wherein said comparator is a one-bit quantizer, said digital-to-analog conversion unit is a one-bit digital-to-analog converter, and a control signal of said comparator is said third clock signal.
8. 8. The Sigma-delta modulator circuit of claim 2 wherein if said modulator circuit is of a multi-bit quantized, high order full feed forward configuration, said integration module performs a high order expansion by adding an integration unit, and said comparator is a multi-bit quantized comparator.
9. 9. The Sigma-delta modulator circuit of claim 1, wherein said input signal is a sensor signal.
10. 10. The Sigma-delta modulator circuit of claim 1 wherein a duration of said third clock signal within each period ranges from greater than one tenth of said period to less than or equal to one fifth of said period.

Description

Sigma-delta modulator circuit Technical Field Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to Sigma-delta modulator circuits. Background Currently, conventional Sigma-delta modulators operate in low supply voltage environments (typically less than 5.5V), but in some practical applications the input common mode voltage can be very high, on the order of tens of V, which can directly damage the modulator if the analog-to-digital conversion is performed directly with a conventional low voltage Sigma-delta modulator. For high input common mode voltage applications, a buffer is inserted between the input signal and the modulator, and the buffer is used to resist the high common mode input voltage, and the output is low voltage and then sent to the ADC for conversion. The disadvantage of this architecture is that a special buffer is required to handle the high common mode input voltage, increasing power consumption and circuit complexity. Disclosure of Invention The embodiments described herein provide Sigma-delta modulator circuits. According to a first aspect of the present disclosure, there is provided a Sigma-delta modulator circuit comprising an integrating module, an adder module, a comparator, a feedback digital-to-analog conversion module; the integrating module performs integrating operation on the difference value between an input signal and the output of a feedback digital-to-analog conversion module to obtain an integrator output result, the adder module performs summation operation on the input signal and the integrator output result, the output of the adder module is connected to the comparator, the output of the comparator is fed back to the integrating module through the feedback digital-to-analog conversion module, the output of the comparator is an output signal, the input signal is a high common mode input signal, a sampling capacitor in a first stage of integrating unit in the integrating module is a high voltage capacitor, the feedback capacitor in the feedback digital-to-analog conversion module is a high voltage capacitor, the adder module receives the input signal through the high voltage capacitor, the modulator circuit performs operation on the first stage of integrating signal, the second stage of integrating signal and the adder module through the high voltage capacitor, the period of the three clock signals is the same, the first clock signal and the second clock signal are two-phase non-overlapping clock signals, the third clock signal is a first clock signal and the adder module performs sampling operation on the first clock signal and the adder module when the first clock signal is a high level, the adder module performs the sampling operation on the first clock signal and the second clock signal, the adder module performs the comparison operation on the high-offset sampling signal, the first stage of the integrating module performs the sampling operation on the first clock signal and the second clock signal, the first clock signal is a high-phase offset sampling operation on the first clock signal, and eliminating the offset voltage, and feeding back the output of the comparator to the integrating module for subtraction operation. In some embodiments of the disclosure, if the modulator circuit is in a one-bit quantized, second-order full feedforward structure, the integrating module includes a first-stage integrating unit and a second-stage integrating unit, where the first-stage integrating unit is connected in series with the second-stage integrating unit, the first-stage integrating unit performs an integrating operation on the input signal, and the second-stage integrating unit performs an integrating operation on an output result of the first-stage integrating unit. In some embodiments of the disclosure, the input signal includes a first input signal and a second input signal, the first stage integrating unit includes four first switches, four second switches, two first sampling capacitors, a first transconductance operational amplifier, and two first integrating capacitors, where two ends of the first switches are respectively connected to one ends of the first input signal and the first sampling capacitor, two ends of the second first switches are respectively connected to one ends of the second input signal and the second first sampling capacitor, a third first switch and a fourth first switch are respectively connected in parallel to two ends of the first transconductance operational amplifier, two ends of the first second switch are respectively connected to one ends of the second input signal and the first sampling capacitor, two ends of the second switch are respectively connected to one ends of the first input signal and the second first sampling capacitor, the third second switch is connected to one end of the first integrating capacitor, and then connected to one end of the second sampling capacitor in