CN-117193448-B - LDO compensation circuit applied to off-chip capacitor

CN117193448BCN 117193448 BCN117193448 BCN 117193448BCN-117193448-B

Abstract

The invention provides an LDO compensation circuit applied to an off-chip capacitor, which belongs to the technical field of circuits and comprises an error amplifier, a buffer and a power tube, wherein the buffer comprises induced current, the power tube comprises a power tube input end and a power tube output end, the input end of the error amplifier is respectively connected with an output reference end and an LDO feedback end, the output end of the error amplifier is connected with the input end of the buffer, the output end of the buffer is connected with the input end of the power tube, and the output end of the power tube is connected with the LDO feedback end. The invention can improve the phase margin of the linear voltage stabilizer and reduce the static power consumption.

Inventors

LI LINYANG
LIU JISHAN
YUN TINGHUA

Assignees

上海川土微电子有限公司

Dates

Publication Date: 20260512
Application Date: 20230828

Claims (8)

1. An LDO compensation circuit for off-chip capacitors, comprising: Error amplifier, buffer and power tube; the buffer includes an input for sensing a sense current of a load current magnitude; The power tube comprises a power tube input end and a power tube output end; the input end of the error amplifier is respectively connected with an output reference end and an LDO feedback end, the output end of the error amplifier is connected with the input end of the buffer, the output end of the buffer is connected with the input end of the power tube, and the output end of the power tube is connected with the LDO feedback end; And when the load current is relatively large, the voltage drop of the fourth resistor R4 is relatively large so as to limit the voltage of the grid electrode of the power tube to be too low, thereby limiting the short-circuit current.
2. The LDO compensation circuit for an off-chip capacitor of claim 1, wherein the first pole is included between the output of the error amplifier and the input of the buffer.
3. The LDO compensation circuit for off-chip capacitors of claim 1, wherein the buffer comprises a second pole between the output and the power transistor input.
4. The LDO compensation circuit of claim 1, wherein a third pole is included between the power transistor output and the LDO feedback.
5. The LDO compensation circuit for off-chip capacitors of claim 2, further comprising a first resistor and a capacitor, the first resistor connected to the buffer through the first pole.
6. The LDO compensation circuit for an off-chip capacitor of claim 4, further comprising a second resistor, wherein the output of the power tube, the input of the second resistor, the output of the second resistor, and the LDO feedback are sequentially connected, and wherein the third pole is located between the output of the power tube and the input of the second resistor.
7. The LDO compensation circuit for off-chip capacitors of claim 2 or 5, wherein the error amplifier employs an operational amplifier architecture of OTA and the miller compensation method is employed to compensate the first pole.
8. The LDO compensation circuit for an off-chip capacitor as recited in claim 6, further comprising a third resistor, wherein one end of the third resistor is grounded, and the other end of the third resistor is connected to an output end of the second resistor.

Description

LDO compensation circuit applied to off-chip capacitor Technical Field The application relates to the technical field of circuits, in particular to an LDO compensation circuit applied to an off-chip capacitor. Background In the prior art, the compensation of LDO (low dropoutregulator, low dropout linear regulator) is generally classified into miller compensation (SMC), damping coefficient control compensation (PFCFC), pole-zero tracking frequency compensation (PLFEC), dynamic miller compensation (DMFC), pole-controlled miller compensation (PCFC), and the like. As is well known, when frequency compensation is applied to a feedback system, positive feedback can cause LDO oscillation, insufficient phase margin can cause prolonged system setup time and poor transient response, so a reliable frequency compensation method is required to ensure the stability of the system and the transient response. To solve this problem, as shown in fig. 1, the LDO circuit in the prior art mainly includes a first stage error amplifier and a power tube, the main pole is at the output pole, the non-main pole is at the output end of the error amplifier, the main pole gradually moves at high frequency with increasing load current, the phase margin gradually decreases, and when the load current is greater than a certain value, the LDO loop is no longer stable. Based on the circuit structure, the traditional method is to improve the stability of the linear voltage stabilizer by modifying the transfer function and simultaneously improve the transient response speed, but the method needs to consume larger static power consumption. Disclosure of Invention The invention provides an LDO compensation circuit applied to an off-chip capacitor, which can reduce the static power consumption of an LDO. The invention provides an LDO compensation circuit applied to an off-chip capacitor, which comprises: Error amplifier, buffer and power tube; the buffer includes an input for sensing a sense current of a load current magnitude; The power tube comprises a power tube input end and a power tube output end; The input end of the error amplifier is respectively connected with the output reference end and the LDO feedback end, the output end of the error amplifier is connected with the input end of the buffer, the output end of the buffer is connected with the input end of the power tube, and the output end of the power tube is connected with the LDO feedback end. Optionally, a first pole is included between the output of the error amplifier and the input of the buffer. Optionally, a second pole is included between the output end of the buffer and the input end of the power tube. Optionally, a third pole is included between the output end of the power tube and the feedback end of the LDO. Optionally, the device further comprises a first resistor and a capacitor, wherein the first resistor is connected with the capacitor, and the first resistor is connected with the buffer through the first pole. Optionally, the power tube further comprises a second resistor, the output end of the power tube, the input end of the second resistor, the output end of the second resistor and the LDO feedback end are sequentially connected, and the third pole is located between the output end of the power tube and the input end of the second resistor. Optionally, the error amplifier adopts an operational amplifier architecture of an OTA, and compensates the first pole by adopting a Miller compensation method. Optionally, the circuit further comprises a third resistor, one end of the third resistor is grounded, and the other end of the third resistor is connected with the output end of the second resistor. The LDO compensation circuit applied to the off-chip capacitor comprises an error amplifier, a buffer and a power tube, wherein the buffer comprises an induction current which is used for inducing the magnitude of load current, the power tube comprises a power tube input end and a power tube output end, the input end of the error amplifier is respectively connected with an output reference end and an LDO feedback end, the output end of the error amplifier is connected with the input end of the buffer, the output end of the buffer is connected with the input end of the power tube, and the output end of the power tube is connected with the LDO feedback end. According to the LDO compensation circuit provided by the invention, the buffer is arranged, and the induced current is arranged in the buffer, so that the phase margin of the linear voltage stabilizer can be improved, and meanwhile, the static power consumption can be reduced. Drawings In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtaine