CN-117200572-B - Triple negative-pressure charge pump and radio frequency switch chip

CN117200572BCN 117200572 BCN117200572 BCN 117200572BCN-117200572-B

Abstract

The invention discloses a triple negative-pressure charge pump and a radio frequency switch chip, which have simple and reasonable structural design, can reduce the occupied area of a capacitor, can meet the voltage driving requirement without arranging an additional auxiliary circuit, and comprise a first-stage negative-pressure charge pump and a second-stage negative-pressure charge pump which are cascaded, wherein the first-stage negative-pressure charge pump comprises a first capacitor, a second capacitor, a first switch unit and a second switch unit, the second-stage negative-pressure charge pump comprises a third capacitor, a fourth capacitor, a third switch unit and a fourth switch unit, the first switch unit, the second switch unit, the third switch unit and the fourth switch unit comprise MOS (metal oxide semiconductor) tubes and diodes D1 and D2, the first switch unit to the fourth switch unit are symmetrically connected in a cross mode, the cathodes of the diodes D1 and D2 are respectively connected with the output ends of the first switch unit to the fourth switch unit, the anodes of the diodes D1 and D2 are respectively connected with one end and the output end of the capacitor, and the radio frequency switch chip comprises the triple negative-pressure charge pump.

Inventors

LIU GANG
DING JIAJIA
JIANG HAIBO
GUO TIANSHENG
ZHAO PENG

Assignees

江苏乾合微电子有限公司

Dates

Publication Date: 20260512
Application Date: 20220531

Claims (7)

1. The triple negative voltage charge pump comprises a primary negative voltage charge pump and a secondary negative voltage charge pump, wherein the primary negative voltage charge pump is cascaded with the secondary negative voltage charge pump, and the primary negative voltage charge pump comprises a first capacitor C1, a second capacitor C2, a first switch unit and a second switch unit, and is characterized in that the secondary negative voltage charge pump comprises a third capacitor C3, a fourth capacitor C4, a third switch unit and a fourth switch unit; the first switch unit comprises MOS tubes M11, M12, M13 and M14, the second switch unit comprises MOS tubes M21, M22, M23 and M24, one end of the first capacitor C1 is connected with a clock signal CLK1, the other end of the first capacitor C1 is respectively connected with an emitter of the MOS tube M11, a collector of the MOS tube M12, an emitter of the MOS tube M23, bases of the MOS tube M13 and M14, one end of a third capacitor C3, a collector of the MOS tube M41, an emitter of the MOS tube M42 and an emitter of the MOS tube M44, one end of the second capacitor C2 is connected with a clock signal CLK2, and the other end of the second capacitor C2 is respectively connected with an emitter of the MOS tube M21, a collector of the MOS tube M22, an emitter of the MOS tube M14, a base of the MOS tube M23 and M24, one end of the fourth capacitor C4, a collector of the MOS tube M31, an emitter of the MOS tube M32 and an emitter of the MOS tube M33; The other end of the third capacitor C3 is respectively connected with the emitter of the MOS tube M31, the collector of the MOS tube M32, the emitter of the MOS tube M43, the bases of the MOS tubes M34 and M33 and the cathode of the diode D1, the other end of the fourth capacitor C4 is respectively connected with the emitter of the MOS tube M41, the collector of the MOS tube M42, the emitter of the MOS tube M34, the bases of the MOS tubes M43 and M44 and the cathode of the diode D2, the anodes of the diodes D1 and D2 are respectively connected with one end of the capacitor C5 and the output end Vneg after being connected, and the other end of the capacitor C5 is grounded.
2. The triple negative voltage charge pump of claim 1 wherein the MOS transistors M11, M21, M14, M23, M31, M41, M34, M43 are NMOS transistors, and the MOS transistors M12, M22, M13, M24, M32, M42, M33, M44 are PMOS transistors.
3. The triple negative charge pump of claim 1 or 2, wherein the clock signals CLK1, CLK2 are generated by a clock circuit, the clock circuit is a non-overlapping clock signal generating circuit comprising MOS transistors M51, M52, M53, M54, logic nor gates F11, F21, logic nor gates F12, F13, F14, F21, F22, F23, F24, the MOS transistors M51 and M52 form a first inverter, the MOS transistors M53 and M54 form a second inverter, bases of the MOS transistors M51, M52 are respectively connected to an output terminal of the logic nor gate F22, an input terminal of the logic nor gate F23, a collector of the MOS transistors M51, M52 is connected to an input terminal 1 port of the logic nor gate F11, an input terminal 2 port of the logic nor gate F11 is connected to the clock signal CLKa, bases of the MOS transistors M53, M54 are respectively connected to an output terminal of the logic nor gate F12, an output terminal of the logic nor gate F13, a collector of the logic nor gate F21, a input terminal of the logic nor gate F21, a 2, a input terminal of the logic nor gate F14, an output terminal of the logic nor gate F21, a signal F2 is connected to the input terminal of the logic nor gate F2, a signal of the logic nor gate F14, a output terminal of the logic nor gate F21, a signal is connected to the input terminal of the logic nor gate F2, a signal of the input terminal of the logic nor gate F23, and a serial connection of the input terminal of the logic nor gate F21, the input of the logic nor gate F2 is connected to the input terminal of the logic n1, and output terminal of the logic n2, and output signal of the input of the logic n2 is serial connection of the logic signal of the input signal n 2.
4. The triple negative voltage charge pump of claim 3, wherein the MOS transistors M51 and M53 are PMOS transistors, and the MOS transistors M52 and M54 are NMOS transistors.
5. The triple negative voltage charge pump of claim 3, wherein the complementary clock signal is generated by a complementary clock signal generating circuit, the complementary clock signal generating circuit comprises MOS transistors M26-M31, gates of the MOS transistors M26 and M29 are all connected to a clock signal CLK, sources of the MOS transistors M26, M27 and M28 are all connected to a voltage source VddH, drains of the MOS transistors M26 are respectively connected to drains of the MOS transistors M29, M27 and M30, and output a clock signal CLKa, drains of the MOS transistors M27 are respectively connected to gates of the MOS transistors M30, M28 and M31, and output a clock signal CLKb, and sources of the MOS transistors M29, M30 and M31 are all grounded.
6. The triple negative voltage charge pump of claim 5, wherein the MOS transistors M26, M27, M28 are PMOS transistors, and the MOS transistors M29, M30, M31 are NMOS transistors.
7. The utility model provides a radio frequency switch chip, its includes drive voltage module, level conversion module, the radio frequency switch that connects gradually, drive voltage module includes positive pressure charge pump, negative pressure charge pump, positive pressure charge pump is used for the level conversion module provides positive pressure, negative pressure charge pump is used for the level conversion module provides negative pressure, the level conversion module is used for with the control voltage that positive pressure, negative pressure converted, control voltage is used for controlling the switch open or close in the radio frequency switch, its characterized in that, negative pressure charge pump is the triple negative pressure charge pump of claim 1, is used for the level conversion module provides the triple negative pressure charge pump.

Description

Triple negative-pressure charge pump and radio frequency switch chip Technical Field The utility model relates to the technical field of radio frequency switches, in particular to a triple negative pressure charge pump and a radio frequency switch chip. Background Currently, a radio frequency device for a communication device includes a radio frequency transceiver, an amplifier, a switch, a power supply, an antenna, and the like, in order to reduce the overall area of the device, a single power line VIO of 1.8V or 1.2V is often used in an MIPI interface (mobile device processor interface) to supply power to the radio frequency switch, and a negative-pressure charge pump is used to raise and reversely convert the VIO voltage, so as to meet the voltage requirement when the radio frequency switch is turned off. The common negative-pressure charge pump comprises a double negative-pressure charge pump and a triple negative-pressure charge pump, wherein the triple negative-pressure charge pump is obtained by cascading two double negative-pressure pumps, but the common triple negative-pressure charge pump at present has the problems of complex structure and large occupied area, and the reason is that in the common cascading double negative-pressure charge pump structure at present, the inverted clock signals CLK1 and CLK2 output by an oscillator need at least four capacitors to realize signal inversion, so that the areas of the four capacitors are kept consistent for ensuring the capacitance performance, the process complexity is increased, and the arrangement of the four capacitors occupies a larger space area in the actual manufacturing process. In addition, the driving voltage of the two-stage cascade circuit is provided by an additional auxiliary circuit, and the arrangement of the auxiliary circuit also increases the area of the whole integrated circuit system, so that the requirements of high integration and miniaturization of the integrated circuit cannot be met. Disclosure of utility model Aiming at the problems in the prior art, the utility model provides the triple negative-pressure charge pump which has simple and reasonable structural design, can reduce the occupied area of a capacitor, and can meet the voltage driving requirement without arranging an additional auxiliary circuit. In order to achieve the above purpose, the utility model adopts the following technical scheme: The triple negative voltage charge pump comprises a primary negative voltage charge pump and a secondary negative voltage charge pump, wherein the primary negative voltage charge pump is cascaded with the secondary negative voltage charge pump, and the primary negative voltage charge pump comprises a first capacitor C1, a second capacitor C2, a first switch unit and a second switch unit, and is characterized in that the secondary negative voltage charge pump comprises a third capacitor C3, a fourth capacitor C4, a third switch unit and a fourth switch unit; the first switch unit comprises MOS tubes M11, M12, M13 and M14, the second switch unit comprises MOS tubes M21, M22, M23 and M24, one end of the first capacitor C1 is connected with a clock signal CLK1, the other end of the first capacitor C1 is respectively connected with an emitter of the MOS tube M11, a collector of the MOS tube M12, an emitter of the MOS tube M23, bases of the MOS tube M13 and M14, one end of a third capacitor C3, a collector of the MOS tube M41, an emitter of the MOS tube M42 and an emitter of the MOS tube M44, one end of the second capacitor C2 is connected with a clock signal CLK2, and the other end of the second capacitor C2 is respectively connected with an emitter of the MOS tube M21, a collector of the MOS tube M22, an emitter of the MOS tube M14, a base of the MOS tube M23 and M24, one end of the fourth capacitor C4, a collector of the MOS tube M31, an emitter of the MOS tube M32 and an emitter of the MOS tube M33; The other end of the third capacitor C3 is respectively connected with the emitter of the MOS tube M31, the collector of the MOS tube M32, the emitter of the MOS tube M43, the bases of the MOS tubes M34 and M33 and the cathode of the diode D1, the other end of the fourth capacitor C4 is respectively connected with the emitter of the MOS tube M41, the collector of the MOS tube M42, the emitter of the MOS tube M34, the bases of the MOS tubes M43 and M44 and the cathode of the diode D2, the anodes of the diodes D1 and D2 are respectively connected with one end of the capacitor C5 and the output end Vneg after being connected, and the other end of the capacitor C5 is grounded. It is further characterized in that, The MOS transistors M11, M21, M14, M23, M31, M41, M34 and M43 are NMOS transistors; the MOS transistors M12, M22, M13, M24, M32, M42, M33 and M44 are PMOS transistors The clock signals CLK1 and CLK2 are generated by a clock circuit, the clock circuit is a non-overlapping clock circuit and comprises MOS tubes M51, M52, M53 and M54, lo