CN-117219615-B - Semiconductor structure and manufacturing method thereof

CN117219615BCN 117219615 BCN117219615 BCN 117219615BCN-117219615-B

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for solving the technical problem of larger contact resistance between a bit line and a bit line plug; a plurality of word lines arranged at intervals and extending in a first direction; the memory device comprises a memory cell array, a plurality of bit lines, a plurality of bit line plugs, a plurality of bit lines, a plurality of bit line storage unit arrays, a plurality of bit line storage unit array and a plurality of bit line storage unit array, wherein the bit lines are arranged at intervals and extend along a second direction, one end of each bit line far away from the memory cell array forms a step in a first direction, each bit line is provided with a groove on the surface of the step, the second direction is mutually intersected with the first direction, and one end of each bit line plug is correspondingly arranged in the groove of one bit line. By providing the grooves on the surface of the bit lines, the contact area between the bit lines and the bit line plugs is increased, and the contact resistance between the bit lines and the bit line plugs is reduced, thereby improving the performance of the semiconductor structure.

Inventors

LIU YOUMING
JIANG YI
XIAO DEYUAN
SHAO GUANGSU

Assignees

长鑫存储技术有限公司

Dates

Publication Date: 20260512
Application Date: 20220531

Claims (14)

1. A semiconductor structure, comprising: A substrate, wherein a first laminated structure is arranged on the substrate, and the first laminated structure comprises a memory cell array; A plurality of word lines arranged at intervals and extending along a first direction, wherein the word lines penetrate through the first laminated structure and are electrically connected with the memory cell array; The memory device comprises a first stacked structure, a plurality of bit lines, a plurality of second stacked structures, a plurality of first storage units, a plurality of second storage units and a plurality of first storage units, wherein the bit lines are arranged at intervals and extend along a second direction, are arranged at the side of the first stacked structure and are electrically connected with the first storage units, one end of each bit line, which is far away from the first storage units, forms a step in the first direction, each bit line is provided with a groove on the surface of the step, and the second direction and the first direction are mutually intersected; A plurality of bit line plugs which are arranged at intervals and extend along the first direction, wherein one end of each bit line plug is correspondingly arranged in the groove of one bit line; The memory cell array includes a plurality of transistors including a source; a drain electrode, wherein one of the source electrode and the drain electrode is electrically connected with the bit line; A plurality of transistors are arranged at intervals along the first direction and at intervals along the second direction, and each transistor extends along a third direction; the third direction is perpendicular to the first direction and the second direction; A plurality of support layers disposed between two rows of the transistors adjacent in the first direction; Wherein the bit line and one of the source electrode and the drain electrode connected thereto are integrally formed.
2. The semiconductor structure of claim 1, wherein at least one of the bit lines is doped N-type or P-type.
3. The semiconductor structure of claim 1, wherein a plurality of said bit line plugs are offset along said second direction.
4. The semiconductor structure of claim 1, wherein the transistor further comprises: The source electrode, the channel and the drain electrode are sequentially arranged along the third direction; the word line surrounds the channel, forming a gate of the transistor; And a dielectric layer disposed between the gate and the channel.
5. The semiconductor structure of claim 4, wherein each of the word lines surrounds a plurality of the channels located in a same column along the first direction; the bit lines are stacked along the first direction, and adjacent bit lines are electrically isolated, and each bit line is connected with the drains positioned in the same row along the second direction.
6. The semiconductor structure of claim 4, wherein the memory cell array further comprises a plurality of capacitors in one-to-one and electrically connected with the other of the source and the drain of the plurality of transistors.
7. The semiconductor structure of any of claims 4-6, wherein the first stack structure further comprises: and the isolation layer is filled in the residual space of the first laminated structure.
8. The semiconductor structure of claim 7, wherein the support layer is disposed between sources of two adjacent rows of the transistors and between drains of two adjacent rows of the transistors.
9. The semiconductor structure of any one of claims 1-6, further comprising a first insulating layer filled between two adjacent bit lines, a first protective layer covering the bit lines and the first insulating layer, and a second insulating layer filled between two adjacent bit line plugs and covering the first stacked structure; and a plurality of word line plugs which are arranged at intervals are arranged in the second insulating layer, and the word line plugs are in one-to-one correspondence with the word lines and are electrically connected.
10. A method of fabricating a semiconductor structure, comprising: Forming a first stacked structure on a substrate, the first stacked structure including a memory cell array; Forming a plurality of word lines which are arranged at intervals on the substrate and extend along a first direction, wherein the word lines penetrate through the first laminated structure and are electrically connected with the memory cell array; forming a plurality of bit lines which are arranged at intervals on the substrate and extend along a second direction, wherein the bit lines are arranged at the side of the first laminated structure and are electrically connected with the memory cell array; a plurality of the bit lines are stepped in the first direction at an end remote from the memory cell array, and each bit line is provided with a groove on the surface of the step, and the first direction and the second direction are mutually intersected; forming a plurality of bit line plugs which are arranged at intervals and extend along the first direction, wherein one end of each bit line plug is correspondingly arranged in a groove of one bit line; Wherein, form a plurality of intervals setting and along the bit line of second direction extension on the substrate, the bit line sets up the side of first stacked architecture and with memory cell array electric connection includes: forming a second laminated structure on the substrate, wherein the second laminated structure is positioned beside the first laminated structure and comprises a first sacrificial layer and a first active layer which are alternately arranged in sequence; Removing a part of the first sacrificial layer and a part of the first active layer far away from the first laminated structure, and forming steps on the rest of the first active layer in the first direction so as to form the bit line; Removing the rest of the first sacrificial layer; The memory cell array includes a plurality of transistors including a source; The first laminated structure further comprises a plurality of support layers, wherein the support layers are formed between two rows of transistors adjacent to each other along the first direction; Wherein the bit line and one of the source electrode and the drain electrode connected thereto are integrally formed.
11. The method of claim 10, further comprising, after removing the remaining first sacrificial layer: And carrying out N-type doping or P-type doping on the bit line to reduce the resistance of the bit line.
12. The method of claim 11, wherein the bit line material comprises silicon; n-type doping or P-type doping is carried out on the bit line so as to reduce the resistance of the bit line, and the method comprises the following steps: doping phosphorus atoms into the bit line by utilizing a thermal diffusion process under the gas phase condition of phosphorus oxychloride, and forming phosphosilicate glass on the surface of the bit line; And removing the phosphosilicate glass to expose the doped bit line.
13. The method of claim 12, wherein the temperature of the thermal diffusion process is 800 ℃ to 1000 ℃; and removing the phosphosilicate glass by utilizing hydrofluoric acid etching.
14. The method of claim 10, wherein forming a plurality of bit line plugs disposed at intervals and extending in the first direction, one end of each bit line plug being disposed in a recess of one bit line, further comprises: forming a first insulating layer filled between the bit lines, and forming a first protective layer covering the bit lines and the first insulating layer; forming a second insulating layer filled between the bit line plugs, the second insulating layer also covering the first stacked structure; and forming a plurality of word line plugs arranged at intervals in the second insulating layer, wherein each word line plug is electrically connected with one word line.

Description

Semiconductor structure and manufacturing method thereof Technical Field The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor structure and a method for manufacturing the same. Background With the development of semiconductor technology, memories, particularly dynamic random access memories (Dynamic Random Access Memory, abbreviated as DRAMs), are widely used in various electronic devices due to their high storage density and high read/write speed. The dram generally includes a plurality of memory cells, each of which includes a transistor and a capacitor, a gate of the transistor is electrically connected to a Word Line (WL) of the dram, on and off of the transistor is controlled by a voltage on the Word Line, one of a source and a drain of the transistor is electrically connected to a Bit Line (BL), and the other of the source and the drain is electrically connected to the capacitor, and data information is stored or output through the Bit Line. In order to reduce the size of the memory and increase its storage density, the capacitor is generally placed horizontally so as to make a capacitor having a larger slenderness ratio. Correspondingly, the transistor is also horizontally arranged, and the transistor is led out to the bit line plug through the bit line so as to be electrically connected with the peripheral circuit. However, the contact resistance between the bit line and the bit line plug is large. Disclosure of Invention In view of the foregoing, embodiments of the present disclosure provide a semiconductor structure and a method for fabricating the same for reducing contact resistance between a bit line and a bit line plug. According to some embodiments, a first aspect of the present disclosure provides a semiconductor structure, which includes a substrate, a first stacked structure disposed on the substrate, the first stacked structure including a memory cell array, a plurality of word lines disposed at intervals and extending in a first direction, the word lines passing through the first stacked structure and electrically connected to the memory cell array, a plurality of bit lines disposed at intervals and extending in a second direction, the bit lines disposed at sides of the first stacked structure and electrically connected to the memory cell array, one end of the bit lines away from the memory cell array forming a step in the first direction, each of the bit lines being provided with a groove on a surface of the step, the second direction intersecting the first direction, and a plurality of bit line plugs disposed at intervals and extending in the first direction, one end of each of the bit line plugs being disposed in the groove of one of the bit lines. In some possible embodiments, at least one of the bit lines is doped N-type or P-type. In some possible embodiments, a plurality of the bit line plugs are arranged offset along the second direction. In some possible embodiments, the memory cell array includes a plurality of transistors arranged at intervals along the first direction and at intervals along the second direction, each of the transistors extending along a third direction, the third direction being perpendicular to both the first direction and the second direction. In some possible embodiments, the transistor comprises a source electrode, a drain electrode, a channel, a word line, a dielectric layer and a dielectric layer, wherein one electrode of the source electrode and the drain electrode is electrically connected with the bit line, the source electrode, the channel and the drain electrode are sequentially arranged along the third direction, the word line surrounds the channel to form a grid electrode of the transistor, and the dielectric layer is arranged between the grid electrode and the channel. In some possible embodiments, each word line surrounds a plurality of the channels located in the same column along the first direction, a plurality of the bit lines are stacked along the first direction, and adjacent bit lines are electrically isolated, and each bit line is connected with a plurality of the drains located in the same row along the second direction. In some possible embodiments, the memory cell array further includes a plurality of capacitors in one-to-one correspondence and electrically connected with the other one of the source and the drain of the plurality of transistors. In some possible embodiments, the first stacked structure further includes a plurality of support layers disposed between two rows of the transistors adjacent in the first direction, and an isolation layer filling a remaining space of the first stacked structure. In some possible embodiments, the support layer is disposed between sources of two adjacent rows of the transistors and between drains of two adjacent rows of the transistors. In some possible embodiments, the semiconductor structure further comprises a first insulating laye