CN-117239685-B - Electrostatic protection structure, silicon controlled rectifier and semiconductor memory

Abstract

The embodiment of the disclosure discloses an electrostatic protection structure, a silicon controlled rectifier and a semiconductor memory, wherein the electrostatic protection structure comprises a substrate; the capacitor is formed in the substrate, the first pole of the capacitor is connected with the substrate, and the second pole of the capacitor is connected with the electrostatic end. The embodiment of the disclosure can rapidly conduct the parasitic BJT formed in the electrostatic protection structure, thereby discharging the electrostatic discharge, playing a good electrostatic protection role and avoiding damaging devices.

Inventors

• XU QIAN

Assignees

• 长鑫存储技术有限公司

Dates

Publication Date

20260508

Application Date

20220608

Claims (14)

1. 1. An electrostatic protection structure, characterized in that the electrostatic protection structure comprises: A substrate; a transistor formed in the substrate, a first pole of the transistor being connected to an electrostatic terminal, a second pole of the transistor and a gate of the transistor both being connected to a charge drain terminal; A capacitor, a first pole of which is connected with the substrate, and a second pole of which is connected with the electrostatic terminal; The substrate is a P-type substrate, the transistor comprises an NMOS tube, and a first pole and a second pole of the NMOS tube are a first N-type doped region and a second N-type doped region which are respectively formed in the P-type substrate; the capacitor comprises a first capacitor, a first pole of the first capacitor is connected with the P-type substrate, and a second pole of the first capacitor is connected with the electrostatic end; The P-type substrate is also provided with a P+ doped region, wherein, The second N-type doped region is positioned between the first N-type doped region and the P+ doped region; the first electrode of the first capacitor is connected with the P-type substrate through the P+ doped region.
2. 2. The electrostatic protection structure of claim 1, wherein the charge draining terminal is a ground terminal, and the P-type substrate is connected to the ground terminal.
3. 3. The electrostatic protection structure of claim 1, further comprising a resistor, wherein, The resistor is connected in series between the grid electrode of the NMOS tube and the charge discharging end.
4. 4. The electrostatic protection structure of claim 1, wherein the substrate is an N-type substrate, the transistor comprises a PMOS transistor, and the first and second poles of the PMOS transistor are first and second P-type doped regions formed in the N-type substrate, respectively.
5. 5. The electrostatic protection structure of claim 4, wherein the N-type substrate further has an N+ doped region formed therein, wherein, The second P-type doped region is located between the first P-type doped region and the N+ doped region.
6. 6. An electrostatic protection structure according to claim 5, wherein, The first pole of the capacitor is connected with the N-type substrate through the N+ doped region.
7. 7. The electrostatic protection structure of claim 4, wherein the charge draining terminal is a supply voltage terminal, and the N-type substrate is connected to the supply voltage terminal.
8. 8. An electrostatic protection structure according to any one of claims 4 to 7, wherein the N-type substrate is disposed in a P-type substrate.
9. 9. An electrostatic protection structure according to any one of claims 1 to 3, wherein an N-type well region is further formed in the P-type substrate, the transistor further comprises a PMOS transistor, the PMOS transistor is disposed in the N-type well region, a first pole and a gate of the PMOS transistor are connected to a power supply voltage terminal, and a second pole of the PMOS transistor is connected to the electrostatic terminal; And the first electrode of the second capacitor is connected with the N-type well region, and the second electrode of the second capacitor is connected with the electrostatic end.
10. 10. The electrostatic protection structure according to claim 9, wherein the first pole and the second pole of the PMOS transistor are a first P-type doped region and a second P-type doped region formed in the N-type well region, respectively, and an n+ doped region is further formed in the N-type well region, and the second P-type doped region is located between the first P-type doped region and the n+ doped region.
11. 11. The electrostatic protection structure of claim 10, wherein a first pole of the second capacitor is connected to the N-type well region through the n+ doped region.
12. 12. The electrostatic protection structure of claim 9, wherein the N-well is connected to the supply voltage terminal.
13. 13. A silicon controlled rectifier comprising an electrostatic protection structure according to any one of claims 1 to 12.
14. 14. A semiconductor memory comprising the electrostatic protection structure according to any one of claims 1 to 12.

Description

Electrostatic protection structure, silicon controlled rectifier and semiconductor memory Technical Field The present disclosure relates to the field of electrostatic protection technologies, and in particular, to an electrostatic protection structure, a silicon controlled rectifier, and a semiconductor memory. Background Various levels of electrostatic discharge (Electro-STATIC DISCHARGE, ESD) occur during the fabrication process of integrated circuit chips as well as during the final system application. ESD is a transient process of filling a large amount of charges into an integrated circuit from outside to inside, and when the integrated circuit discharges, high voltage of hundreds or even thousands of volts is generated, which easily damages a chip. Currently, the manufacturing process of semiconductors is more advanced, the channel length is shorter, the junction depth (junction depth) is shallower, the oxide layer is thinner, the window of the ESD protection design is smaller, and the challenges of the ESD protection design are larger. Disclosure of Invention The embodiment of the disclosure provides an electrostatic protection structure, a silicon controlled rectifier and a semiconductor memory: in a first aspect, embodiments of the present disclosure provide an electrostatic protection structure, the electrostatic protection structure comprising: A substrate; a transistor formed in the substrate, a first pole of the transistor being connected to an electrostatic terminal, a second pole of the transistor and a gate of the transistor both being connected to a charge drain terminal; and the first electrode of the capacitor is connected with the substrate, and the second electrode of the capacitor is connected with the electrostatic end. In some embodiments, the substrate is a P-type substrate, the transistor comprises an NMOS transistor, and the first and second poles of the NMOS transistor are first and second N-type doped regions formed in the P-type substrate, respectively; The capacitor comprises a first capacitor, a first pole of the first capacitor is connected with the P-type substrate, and a second pole of the first capacitor is connected with the electrostatic end. In some embodiments, the P-type substrate also has a P+ doped region formed therein, wherein, The second N-type doped region is located between the first N-type doped region and the P+ doped region. In some embodiments, a first pole of the first capacitor is connected to the P-type substrate through the p+ doped region. In some embodiments, the charge bleed terminal is a ground terminal, and the P-type substrate is connected to the ground terminal. In some embodiments, the electrostatic protection structure further comprises a resistor, wherein, The resistor is connected in series between the grid electrode of the NMOS tube and the charge discharging end. In some embodiments, the substrate is an N-type substrate, the transistor includes a PMOS transistor, and the first and second poles of the PMOS transistor are first and second P-type doped regions, respectively, formed in the N-type substrate. In some embodiments, the N-type substrate further has an N+ doped region formed therein, wherein, The second P-type doped region is located between the first P-type doped region and the N+ doped region. In some embodiments, a first pole of the capacitor is connected to the N-type substrate through the n+ doped region. In some embodiments, the charge draining terminal is a supply voltage terminal, and the N-type substrate is connected to the supply voltage terminal. In some embodiments, the N-type substrate is disposed in a P-type substrate. In some embodiments, an N-type well region is further formed in the P-type substrate, the transistor further includes a PMOS transistor, the PMOS transistor is disposed in the N-type well region, a first pole and a gate of the PMOS transistor are connected to a power supply voltage terminal, and a second pole of the PMOS transistor is connected to the electrostatic terminal; And the first electrode of the second capacitor is connected with the N-type well region, and the second electrode of the second capacitor is connected with the electrostatic end. In some embodiments, the first pole and the second pole of the PMOS transistor are a first P-type doped region and a second P-type doped region formed in the N-type well region, respectively, an n+ doped region is further formed in the N-type well region, and the second P-type doped region is located between the first P-type doped region and the n+ doped region. In some embodiments, the first pole of the second capacitor is connected to the N-type well region through the n+ doped region. In some embodiments, the N-well region is connected to the supply voltage terminal. In a second aspect, embodiments of the present disclosure provide a silicon controlled rectifier comprising an electrostatic protection structure as defined in any one of the first aspects.