CN-117289324-B - Control method and control device of flat panel detector and flat panel detector

CN117289324BCN 117289324 BCN117289324 BCN 117289324BCN-117289324-B

Abstract

According to the control method, the control device and the flat panel detector, the shift registers are divided into the cascade groups, and different cascade groups are coupled with different frame start signal lines and different clock signal lines, so that different working states of each cascade group in different reading modes can be controlled according to different reading modes. In addition, in the first reading mode, the effect of progressive scanning and progressive reading can be realized. In the second reading mode, the effect of simultaneous scanning of multiple rows and simultaneous reading of multiple rows can be realized, and the purposes of reducing the reading time and improving the acquisition frame frequency are achieved.

Inventors

LI JINYU
HOU XUECHENG
DING ZHI
PANG FENGCHUN
DING DING

Assignees

京东方科技集团股份有限公司
北京京东方传感技术有限公司

Dates

Publication Date: 20260505
Application Date: 20220616

Claims (11)

1. A control method of a flat panel detector is characterized in that the flat panel detector comprises a plurality of grid lines, a plurality of data lines, a detection unit, a grid driving circuit, a plurality of frame start signal lines and a plurality of clock signal lines, wherein the data lines are arranged in an insulating and intersecting mode with the grid lines; the grid driving circuit comprises a plurality of shift registers, one shift register is coupled with one grid line, the shift registers are divided into a plurality of cascade groups, the shift registers in the same cascade group are arranged in a cascade manner, and different cascade groups are coupled with different frame start signal lines and different clock signal lines; the control method comprises the following steps: when a first reading mode is adopted, loading different frame starting signals to each frame starting signal line in a frame scanning time, loading different clock signals to each clock signal line, controlling each cascade group to sequentially work, scanning a plurality of grid lines line by line, respectively collecting detection signals on each data line during the grid line scanning, and determining a target detection signal corresponding to each detection unit one by one, wherein each shift register in the same cascade group scans the coupled grid lines line by line; When a second reading mode is adopted, loading the same frame start signal to frame start signal lines coupled with at least part of cascade groups and loading the same clock signal to clock signal lines coupled with at least part of cascade groups in a frame scanning time, controlling the at least part of cascade groups to work simultaneously, scanning a plurality of adjacent grid lines in the grid lines simultaneously, collecting detection signals on the data lines during grid line scanning, and determining target detection signals corresponding to the detection unit groups one by one, wherein the detection unit groups comprise detection units coupled with the grid lines which are scanned simultaneously and coupled with at least one data line, and each shift register pair in the same cascade group scans the coupled grid lines line row by row.
2. The method of controlling a flat panel detector according to claim 1, wherein the plurality of shift registers are divided into N cascade groups, each shift register in the same cascade group is respectively coupled with grid lines separated by N-1 rows, N is an integer greater than 1; The loading the same frame start signal to the frame start signal lines coupled to at least part of the cascade groups and loading the same clock signal to the clock signal lines coupled to at least part of the cascade groups, controlling the at least part of the cascade groups to operate simultaneously, and scanning adjacent gate lines of the gate lines simultaneously, including: and taking at least two adjacent gate lines as a gate line group, loading the same frame start signal to a frame start signal line corresponding to a cascade group coupled with the gate line group, loading the same clock signal to a clock signal line corresponding to the cascade group coupled with the gate line group, controlling the cascade group coupled with the gate line group to work simultaneously, and scanning the gate lines in the gate line group simultaneously.
3. The method of controlling a flat panel detector according to claim 2, wherein cascade groups to which two adjacent gate line groups are coupled are different, wherein for a first gate line group and a second gate line group of the two adjacent gate line groups, different frame start signals are loaded to a cascade group to which the first gate line group is coupled and a frame start signal line corresponding to the cascade group to which the second gate line group is coupled, and different clock signals are loaded to a clock signal line corresponding to the cascade group to which the first gate line group is coupled and the cascade group to which the second gate line group is coupled, the cascade group to which the first gate line group is coupled and the cascade group to which the second gate line group is coupled are controlled to sequentially operate, and the first gate line group and the second gate line group are sequentially scanned.
4. The method of claim 2, wherein two adjacent gate line groups are coupled in the same cascade group, the same frame start signal is loaded on the frame start signal lines corresponding to all the cascade groups, and the same clock signal is loaded on the clock signal lines corresponding to all the cascade groups, so as to control all the cascade groups to operate simultaneously, and all the gate lines in the same gate line group are scanned simultaneously.
5. The control method of the flat panel detector according to claim 3 or 4, wherein n=4, the plurality of clock signal lines includes 1 st clock signal line to 8 th clock signal line, and the plurality of frame start signal lines includes 1 st frame start signal line to 4 th frame start signal line; The cascade groups comprise 1 st cascade group to 4 th cascade group, wherein the 1 st cascade group is coupled with 4k-3 th grid line, the 2 nd cascade group is coupled with 4k-2 th grid line, the 3 rd cascade group is coupled with 4k-1 st grid line, the 4 th cascade group is coupled with 4k grid line, k is an integer larger than 0, and the 1 st cascade group is respectively coupled with 1 st clock signal line, 5 th clock signal line and 1 st frame start signal line, the 2 nd cascade group is respectively coupled with 2 nd clock signal line, 6 th clock signal line and 2 nd frame start signal line, the 3 rd cascade group is respectively coupled with 3 rd clock signal line, 7 th clock signal line and 3 rd frame start signal line, and the 4 th cascade group is respectively coupled with 4 th clock signal line, 8 th clock signal line and 4 th frame start signal line; When the cascade groups coupled by two adjacent gate line groups are different, the first gate line group is coupled with the 1 st cascade group and the 2 nd cascade group, the second gate line group is coupled with the 3 rd cascade group and the 4 th cascade group, the same frame start signal is loaded on the 1 st frame start signal line and the 2 nd frame start signal line, the same clock signal is loaded on the 1 st clock signal line and the 2 nd clock signal line, the same clock signal is loaded on the 5 th clock signal line and the 6 th clock signal line, the same frame start signal is loaded on the 3 rd frame start signal line and the 4 th frame start signal line, the same clock signal is loaded on the 3 rd clock signal line and the 4 th clock signal line, and the same clock signal is loaded on the 7 th clock signal line and the 8 th clock signal line; when two adjacent gate line groups are coupled in cascade, each gate line group is coupled with the 1 st cascade group to the 4 th cascade group, and the same frame start signal is loaded on the 1 st frame start signal line to the 4 th frame start signal line, the same clock signal is loaded on the 1 st clock signal line to the 4 th clock signal line, and the same clock signal is loaded on the 5 th clock signal line to the 8 th clock signal line.
6. The method of claim 5, wherein the active level of the frame start signal loaded by the frame start signal line corresponding to the cascade group coupled to the first gate line group is 1/4 clock period earlier than the active level of the frame start signal loaded by the frame start signal line corresponding to the cascade group coupled to the second gate line group; The clock signal loaded by the clock signal wire corresponding to the cascade group coupled with the first grid line group is the same as the clock period of the clock signal loaded by the clock signal wire corresponding to the cascade group coupled with the second grid line group, and the duty ratio of the clock signal loaded by the clock signal wire corresponding to the cascade group coupled with the first grid line group is 25%.
7. The method according to any one of claims 1 to 4, wherein when the second reading mode is adopted, target detection signals corresponding to groups of detection units one by one are determined based on a rule that detection signals on adjacent M data lines are collected simultaneously to obtain one target detection signal, wherein 2≤m≤m, M is the number of gate lines scanned simultaneously, and the groups of detection units include detection units coupled to the gate lines scanned simultaneously and to the M data lines.
8. The method of controlling a flat panel detector according to any one of claims 1 to 4, wherein a cascade group coupled to an odd-numbered gate line is disposed at a first end of the plurality of gate lines, and a cascade group coupled to an even-numbered gate line is disposed at a second end of the plurality of gate lines.
9. A control device of a flat panel detector is characterized in that the flat panel detector comprises a plurality of grid lines, a plurality of data lines, a detection unit, a grid driving circuit, a plurality of frame start signal lines and a plurality of clock signal lines, wherein the data lines are arranged in an insulating and intersecting mode with the grid lines; the grid driving circuit comprises a plurality of shift registers, one shift register is coupled with one grid line, the shift registers are divided into a plurality of cascade groups, the shift registers in the same cascade group are arranged in a cascade manner, and each cascade group is respectively coupled with a different frame start signal line and a different clock signal line; the control device includes: The driving circuit is configured to load different frame start signals to each frame start signal line, load different clock signals to each clock signal line, control each cascade group to sequentially work and scan the grid lines line by line in a first reading mode, load the same frame start signals to the frame start signal lines coupled to at least part of cascade groups and load the same clock signals to the clock signal lines coupled to at least part of cascade groups in a frame scanning time to control the at least part of cascade groups to work simultaneously and scan the adjacent grid lines in the grid lines simultaneously in a second reading mode, wherein each shift register in the same cascade group scans the coupled grid lines by line; The system comprises a first reading mode, a second reading mode, a data line scanning and a detection unit group, wherein the first reading mode is used for scanning the data line, the second reading mode is used for scanning the data line, the detection unit group comprises detection units which are coupled with the simultaneously scanned data line and coupled with at least one data line, the acquisition circuit is used for acquiring detection signals on the data line respectively when the first reading mode is used for scanning the data line, and determining target detection signals corresponding to each detection unit one by one, and when the second reading mode is used for scanning the data line, the detection signals on the data line are acquired, and the target detection signals corresponding to the detection unit group one by one are determined.
10. The control device of flat panel detector according to claim 9, wherein the plurality of shift registers are divided into N cascade groups, and the shift registers in the same cascade group are respectively coupled with grid lines separated by N-1 rows, wherein N is an integer greater than 1; The driving circuit is further configured to load the same frame start signal to a frame start signal line corresponding to a cascade group coupled to the gate line group and load the same clock signal to a clock signal line corresponding to the cascade group coupled to the gate line group for one gate line group with at least two adjacent gate lines as one gate line group, to control the cascade group coupled to the gate line group to operate simultaneously, and to scan the gate lines in the gate line group simultaneously.
11. A flat panel detector apparatus comprising a flat panel detector and a control apparatus for a flat panel detector as claimed in claim 9 or 10.

Description

Control method and control device of flat panel detector and flat panel detector Technical Field The disclosure relates to the technical field of detection, and in particular relates to a control method and a control device of a flat panel detector and the flat panel detector. Background Radiography uses the short wavelength, penetrating nature of X-rays, and the different absorption of X-rays by different tissues to image by detecting the intensity of X-rays transmitted through an object. A flat panel Detector (FLAT PANEL Detector, FPD) is used as a core component of the X-ray imaging system, and is responsible for converting X-rays into electrical signals and recording the images, and can be displayed by a display or stored for subsequent reading. Disclosure of Invention The control method and the control device for the flat panel detector and the flat panel detector provided by the embodiment of the disclosure can reduce the reading time. The control method of the flat panel detector comprises a plurality of grid lines, a plurality of data lines, a detection unit, a grid driving circuit, a plurality of frame start signal lines and a plurality of clock signal lines, wherein the data lines are arranged in an insulating and intersecting mode with the grid lines; the grid driving circuit comprises a plurality of shift registers, one shift register is coupled with one grid line, the shift registers are divided into a plurality of cascade groups, the shift registers in the same cascade group are arranged in a cascade manner, and different cascade groups are coupled with different frame start signal lines and different clock signal lines; the control method comprises the following steps: when a first reading mode is adopted, loading different frame starting signals to each frame starting signal line in a frame scanning time, loading different clock signals to each clock signal line, controlling each cascade group to sequentially work, scanning a plurality of grid lines line by line, respectively collecting detection signals on each data line during the grid line scanning, and determining a target detection signal corresponding to each detection unit one by one, wherein each shift register in the same cascade group scans the coupled grid lines line by line; When a second reading mode is adopted, loading the same frame start signal to frame start signal lines coupled with at least part of cascade groups and loading the same clock signal to clock signal lines coupled with at least part of cascade groups in a frame scanning time, controlling the at least part of cascade groups to work simultaneously, scanning a plurality of adjacent grid lines in the grid lines simultaneously, collecting detection signals on the data lines during grid line scanning, and determining target detection signals corresponding to the detection unit groups one by one, wherein the detection unit groups comprise detection units coupled with the grid lines which are scanned simultaneously and coupled with at least one data line, and each shift register pair in the same cascade group scans the coupled grid lines line row by row. In some possible embodiments, the plurality of shift registers are divided into N cascade groups, and each shift register in the same cascade group is respectively coupled with grid lines separated by N-1 rows; The loading the same frame start signal to the frame start signal lines coupled to at least part of the cascade groups and loading the same clock signal to the clock signal lines coupled to at least part of the cascade groups, controlling the at least part of the cascade groups to operate simultaneously, and scanning adjacent gate lines of the gate lines simultaneously, including: and taking at least two adjacent gate lines as a gate line group, loading the same frame start signal to a frame start signal line corresponding to a cascade group coupled with the gate line group, loading the same clock signal to a clock signal line corresponding to the cascade group coupled with the gate line group, controlling the cascade group coupled with the gate line group to work simultaneously, and scanning the gate lines in the gate line group simultaneously. In some possible embodiments, cascade groups coupled to two adjacent gate line groups are different, different frame start signals are loaded to a cascade group coupled to the first gate line group and a cascade group coupled to the second gate line group for a first gate line group and a second gate line group of the two adjacent gate line groups, different clock signals are loaded to a clock signal line corresponding to the cascade group coupled to the first gate line group and the cascade group coupled to the second gate line group, and the cascade group coupled to the first gate line group and the cascade group coupled to the second gate line group are controlled to sequentially operate, and sequentially scan the first gate line group and the second gate line group.