Search

CN-117316233-B - Memory device and ZQ calibration method

CN117316233BCN 117316233 BCN117316233 BCN 117316233BCN-117316233-B

Abstract

The embodiment of the disclosure relates to the field of semiconductor circuit design, in particular to a memory device and a ZQ calibration method, wherein the memory device comprises a master chip and a plurality of slave chips, wherein the master chip is provided with a first transmission end and a second transmission end, the first transmission end is connected with each other, the second transmission end is connected with each other, a first signal receiver and an address transmitter are arranged in the master chip, a second signal receiver is arranged in the slave chip, the first signal receiver is used for receiving a ZQ calibration command, the master chip starts calibration based on the ZQ calibration command, the master chip transmits a ZQ mark signal after the calibration is completed, the address transmitter transmits an address signal, the second signal receiver is used for matching the address signal and receiving the ZQ mark signal, the slave chip matched with the address signal starts calibration based on the ZQ mark signal, the current slave chip transmits the ZQ mark signal after the calibration is completed, and the address transmitter transmits the next address signal. The embodiment of the disclosure realizes the sharing of ZQ calibration resistance by designing a new control circuit.

Inventors

  • TIAN KAI

Assignees

  • 长鑫存储技术有限公司

Dates

Publication Date
20260508
Application Date
20220622

Claims (14)

  1. 1. A memory device, comprising: a master chip and a plurality of slave chips, the master chip and the slave chips being commonly connected to the same calibration resistor; the master chip and the slave chip are provided with a first transmission end and a second transmission end, the first transmission ends of the master chip and the slave chip are connected with each other, and the second transmission ends are connected with each other; The first transmission end is used for transmitting the ZQ mark signal, and the second transmission end is used for transmitting the address signal; The master chip is provided with a first signal receiver and an address transmitter, and the slave chip is provided with a second signal receiver; The first signal receiver is used for receiving a ZQ calibration command provided by the memory through a ZQ signal end, the main chip starts calibration based on the ZQ calibration command, the main chip sends the ZQ mark signal through the first transmission end after calibration is completed, and the ZQ mark signal represents that the current chip is calibrated by using the calibration resistor; The address transmitter transmits an address signal through the second transmission end, wherein the address signal represents the address of the slave chip to be subjected to ZQ calibration; The second signal receiver is used for matching the address signal, receiving the ZQ mark signal through a first transmission end, starting calibration of the slave chip matching the address signal based on the ZQ mark signal, and transmitting the ZQ mark signal through the first transmission end after the slave chip finishes calibration; And the address transmitter continuously transmits a next address signal through the second transmission end until the calibration of all the slave chips is completed.
  2. 2. The memory device of claim 1, wherein the address transmitter comprises: An address storage unit for storing address signals of all the slave chips; and the address transmitting unit is connected with the address storage unit and is configured to sequentially transmit the address signals of the slave chips.
  3. 3. The memory device of claim 2, wherein the address transmitter further comprises: and the address sorting unit is connected with the address storage unit and the address transmitting unit and is configured to sort all the address signals, and the address transmitting unit sequentially transmits the sorted address signals.
  4. 4. A memory device according to any one of claims 1 to 3, wherein the address transmitter sequentially transmits the address signals of the slave chips in response to the ZQ flag signal.
  5. 5. A memory device according to any one of claims 1 to 3, wherein the master chip is further configured to send a flag signal indicating that all chips have completed ZQ calibration after the ZQ flag signal is released by the last slave chip to complete ZQ calibration.
  6. 6. The memory device of claim 1, comprising: the first signal receiver includes: The first AND gate, one input end is used for receiving the ZQ calibration command, the other input end is used for receiving a command indication signal, and the command indication signal is used for representing that the memory works in a command mode; the second AND gate, one input end is used for receiving the clock signal or the power-on signal, the other input end is used for receiving the background indication signal, and the background indication signal is used for representing that the memory works in a background mode; The first input selector is connected with the output end of the first AND gate, the second input end is connected with the input end of the second AND gate, the first selector is used for receiving the command indication signal or the background indication signal, the first output end is used for outputting a first internal calibration signal, and the first internal calibration signal is used for indicating the main chip to calibrate; wherein the first input selector is configured to connect the first input to the first output based on the command indication signal or to connect the second input to the first output based on the background indication signal; the second signal receiver includes: The judging unit is used for receiving the address signal transmitted by the second transmission end, acquiring the address signal of the slave chip, and transmitting a first indication signal if the address signal transmitted by the second transmission end is identical to the address signal of the slave chip; And the third AND gate is used for receiving the ZQ mark signal at one input end, receiving the first indication signal at the other input end, outputting a second internal calibration signal at the output end, and indicating the slave chip to calibrate by the second internal calibration signal.
  7. 7. The memory device of claim 6, comprising: the master chip further comprises the second signal receiver, and the slave chip further comprises the first signal receiver; The master chip and the slave chip further comprise a second input selector, a third input end is connected with the first output end, a fourth input end is connected with the output end of the third AND gate, a second selection end is used for receiving a second indication signal or a third indication signal, the second indication signal is used for representing that the current chip is the master chip, the third indication signal is used for representing that the current chip is the slave chip, the second output end is used for outputting the first internal calibration signal and the second internal calibration signal, and the second input selector is configured to connect the third input end to the second output end based on the second indication signal or connect the fourth input end to the second output end based on the third indication signal.
  8. 8. The memory device of claim 1, wherein the master chip and the slave chip are packaged in the same memory device.
  9. 9. The memory device of claim 1, wherein the master chip and a portion of the slave chip are packaged in different memory devices, wherein the connection between the first transmission terminals and the connection between the second transmission terminals packaged in different memory devices are provided by wired or wireless interconnection between memory devices.
  10. 10. The memory device according to claim 1, wherein the number of slave chips is the same as the number of binary data contained in the address signal.
  11. 11. A ZQ calibration method applied to the memory device of any of claims 1-10, comprising: in a command mode, acquiring a ZQ calibration command externally applied to the memory device, or in a background mode, acquiring a clock signal or a power-on signal externally applied to the memory device; performing a first calibration operation on a master chip in response to the ZQ calibration command, the clock signal, or the power-on signal; After the first calibration operation is completed, a ZQ mark signal and an address signal are sent, and a second calibration operation is carried out on the main chip at the same time; A slave chip conforming to the address signal performs a first calibration operation in response to the ZQ flag signal; After the first calibration operation of the slave chip is completed, transmitting the ZQ flag signal, and simultaneously executing the second calibration operation on the slave chip; The master chip resends the address signal, and the slave chips meeting the address signal respond to the ZQ mark signal to execute a first calibration operation until all the slave chips complete the first calibration operation; and completing the second calibration operation on the slave chip which finally completes the first calibration operation.
  12. 12. The ZQ calibration method of claim 11, wherein the master chip transmits the address signal in response to the ZQ flag signal.
  13. 13. The ZQ calibration method of claim 11, wherein the master chip sequentially transmits the ordered address signals based on an ordering of all the address signals.
  14. 14. The ZQ calibration method according to claim 11, wherein the master chip resends address signals further comprises sending a flag signal to indicate that all chips have completed ZQ calibration after the master chip has completed sending all of the address signals.

Description

Memory device and ZQ calibration method Technical Field The present disclosure relates to the field of semiconductor circuit design, and more particularly to a memory device and ZQ calibration method. Background ZQ calibration is a very important function in a dynamic random access memory (Dynamic Random Access Memory, DRAM), and specifically relates to whether the output impedance of an output port is accurate or not, whether the termination resistance of an input port is accurate or not, and the deviation of these parameters can cause serious distortion caused by impedance mismatch in the signal transmission process, and the higher the signal frequency, the greater the influence of the distortion on the signal. The number of ZQ calibration resistors required by LPDDR5 has been specified in the packaging definition of JEDEC, for example, one ZQ calibration resistor is provided in DIS315 type chips and two ZQ calibration resistors are provided in POP496 type chips, so that the number of ZQ calibration resistors in LPDDR5 is obviously smaller than that in LPDDR 4. Along with the increasing demand for LPDDR capacity, more and more chips are put into one packaging body of the LPDDR, and each chip needs to be subjected to independent ZQ calibration due to individual difference, especially the packaging of the LPDDR5, the number of the ZQ calibration resistors is obviously reduced compared with the number of the ZQ calibration resistors in the LPDDR4, more chips need to share one ZQ, and how to realize the ZQ calibration by sharing the ZQ calibration resistors by multiple chips is a technical problem to be solved currently. Disclosure of Invention Embodiments of the present disclosure provide a memory device and a ZQ calibration method that implement a multi-chip shared ZQ calibration resistor by designing a new control circuit. The embodiment of the disclosure provides a memory device, which comprises a master chip and a plurality of slave chips, wherein the master chip and the slave chips are commonly connected to the same calibration resistor, the master chip and the slave chips are provided with a first transmission end and a second transmission end, the first transmission end and the second transmission end are mutually connected, the first transmission end is used for transmitting ZQ mark signals, the second transmission end is used for transmitting address signals, a first signal receiver and an address transmitter are arranged in the master chip, a second signal receiver is arranged in the slave chip, the first signal receiver is used for receiving ZQ calibration commands provided by a memory through the ZQ signal ends, the master chip starts calibration based on the ZQ calibration commands, the master chip transmits ZQ mark signals through the first transmission end after calibration is completed, the ZQ mark signals represent that the current chip is calibrated by using the calibration resistor, the address transmitter transmits address signals through the second transmission end, the address signals represent addresses of the slave chips to be subjected to ZQ calibration, the second signal receiver is used for matching the address signals, the first signal transmission end receives the ZQ mark signals, the address signals are transmitted through the first transmission end, and the slave chip continues to complete calibration of the current calibration signals through the first transmission end after the first transmission end and the address signals are continuously transmitted through the second transmission end. In the memory device provided by the embodiment of the disclosure, the first transmission ends of the master chip and all the slave chips are commonly connected with the same bus, the second transmission ends of the master chip and all the slave chips are commonly connected with the same bus, namely, the master chip and all the slave chips pass through the two buses to form a broadcast loop, in the process of executing ZQ calibration, the master chip firstly carries out ZQ calibration, after the master chip completes ZQ calibration, an address of one slave chip is broadcast, the address of the slave chip with the matched address responds to the broadcast address, ZQ calibration is carried out based on the ZQ mark signal, after the slave chip completes ZQ calibration, the ZQ mark signal is released, and the master chip continues broadcasting the address of the other slave chip until all the slave chips complete ZQ calibration. All chips are connected to two buses, simplifying the design of the memory device package substrate. In addition, the address transmitter includes an address storage unit for storing address signals of all the slave chips, and an address transmitting unit connected to the address storage unit and configured to sequentially transmit the address signals of the slave chips. In addition, the address transmitter further comprises an address ordering unit, which is connected