CN-117316254-B - Memory device and ZQ calibration method

CN117316254BCN 117316254 BCN117316254 BCN 117316254BCN-117316254-B

Abstract

The embodiment of the disclosure relates to the field of semiconductor circuit design, in particular to a memory device and a ZQ calibration method, which comprise two calibration resistor interfaces connected with the same ZQ calibration resistor, a first master chip, a first slave chip, a second master chip and a second slave chip which are commonly connected with the ZQ calibration resistor, wherein in a command mode, a first signal receiver is used for receiving a ZQ calibration command, a second signal receiver is used for receiving and delaying the ZQ calibration command, the first master chip and the second master chip start calibration based on the ZQ calibration command, the first master chip and the second master chip send ZQ mark signals through a second transmission end after calibration is completed, a third signal receiver is used for receiving the ZQ mark signals through a first transmission end, the first slave chip and the second slave chip start calibration based on the ZQ mark signals, and the first slave chip and the second slave chip send the ZQ mark signals through the second transmission end after calibration is completed.

Inventors

TIAN KAI

Assignees

长鑫存储技术有限公司

Dates

Publication Date: 20260508
Application Date: 20220622

Claims (15)

1. A memory device, comprising: the two calibration resistor interfaces are connected with the same ZQ calibration resistor; a first master chip, a plurality of cascaded first slave chips, a second master chip, and a plurality of cascaded second slave chips that are commonly connected to the ZQ calibration resistor; The first master chip, the first slave chip, the second master chip and the second slave chip are provided with a first transmission end and a second transmission end, and the first transmission end and the second transmission end are used for transmitting ZQ mark signals; The second transmission end of the first master chip is connected with the first transmission end of the first slave chip of the first stage, the second transmission end of the first slave chip of each stage is connected with the first transmission end of the first slave chip of the next stage, the second transmission end of the second master chip is connected with the first transmission end of the second slave chip of the first stage, and the second transmission end of the second slave chip of each stage is connected with the first transmission end of the second slave chip of the next stage; A first signal receiver is arranged in the first master chip, a second signal receiver is arranged in the second master chip, and a third signal receiver is arranged in the first slave chip and the second slave chip; in a command mode, the first signal receiver is used for receiving a ZQ calibration command provided by the memory through a ZQ signal end, the second signal receiver is used for receiving and delaying the ZQ calibration command through the ZQ signal end, the first main chip and the second main chip start calibration based on the ZQ calibration command, the first main chip and the second main chip send the ZQ mark signal through the second transmission end after calibration is completed, and the ZQ mark signal represents that the current chip is calibrated by using the calibration resistor; The third signal receiver is configured to receive the ZQ flag signal through the first transmitting end, the first slave chip and the second slave chip start calibration based on the ZQ flag signal, and after the first slave chip and the second slave chip complete calibration, the second transmitting end sends the ZQ flag signal until all the first slave chip or the second slave chip complete calibration.
2. The memory device of claim 1, comprising: the second transmission end of the first slave chip at the last stage is connected with the first transmission end of the first master chip; And the second transmission end of the second slave chip at the last stage is connected with the first transmission end of the second master chip.
3. The memory device of claim 2, comprising: the second master chip further comprises a third transmission end which is started in a background mode and is used for receiving the ZQ mark signal, and the third transmission end is connected with the second transmission end of the first slave chip of the last stage; In the background mode, the first signal receiver is used for receiving a clock signal or a power-on signal provided by the memory through a ZQ signal end, the first main chip starts calibration based on the clock signal or the power-on signal, and the first main chip sends the ZQ mark signal through the second transmission end after calibration is completed; The first slave chip, the second master chip, and the second slave chip start calibration in sequence based on the ZQ flag signal.
4. The memory device of claim 3, wherein the first master chip further comprises a fourth transmission terminal that is turned on in a background mode for transmitting the ZQ flag signal, the fourth transmission terminal being connected to the second transmission terminal of the second slave chip of the last stage.
5. The memory device of claim 3, comprising: the first signal receiver includes: The first AND gate, one input end is used for receiving the ZQ calibration command, the other input end is used for receiving a command indication signal, and the command indication signal is used for representing that the memory works in a command mode; the second AND gate, one input end is used for receiving the clock signal or the power-on signal, the other input end is used for receiving the background indication signal, and the background indication signal is used for representing that the memory works in a background mode; The first input selector is connected with the output end of the first AND gate, the second input end is connected with the output end of the second AND gate, the first selector is used for receiving the command indication signal or the background indication signal, the first output end is used for outputting a first internal calibration signal, and the first internal calibration signal is used for indicating the first main chip and the second main chip to calibrate; wherein the first input selector is configured to connect the first input to the first output based on the command indication signal or to connect the second input to the first output based on the background indication signal; the second signal receiver includes: The third AND gate, one input end is used for receiving and delaying the ZQ calibration command, and the other input end is used for receiving the command indication signal; a fourth AND gate, one input end is used for receiving the ZQ mark signal, and the other input end is used for receiving the background indication signal; The second input selector, the third input end connects the output end of the said third AND gate, the fourth input end connects the output end of the said fourth AND gate, the second selector is used for receiving the said command indication signal or said background indication signal, the second output end is used for outputting the said first internal calibration signal; wherein the second input selector is configured to connect the third input to the second output based on the command indication signal or to connect the fourth input to the second output based on the background indication signal; The third signal receiver includes: and a fifth AND gate, one input end is used for receiving the ZQ mark signal, the other input end is used for receiving a first indication signal, the first indication signal is used for representing that the current chip is the first slave chip or the second slave chip, the output end is used for outputting a second internal calibration signal, and the second internal calibration signal is used for indicating that the first slave chip and the second slave chip are calibrated.
6. The memory device of claim 3, comprising: the first signal receiver and the second signal receiver include: the device comprises a first selector, a second selector, a first selector and a second selector, wherein one input end is used for receiving the ZQ calibration command, the other input end is used for receiving the delayed ZQ calibration command, and the selection end is used for receiving a first main chip identification signal or a second main chip identification signal; The first AND gate has one input end connected to the output end of the first selector and the other input end for receiving command indication signal for representing that the memory is in command mode; The second selector, one input end is used for receiving the clock signal or power-on signal, another input end is used for receiving the ZQ mark signal transmitted by the third transmission end, the selector is used for receiving the first main chip identification signal or the second main chip identification signal; the second selector is configured to output the clock signal or the power-on signal based on the first master chip identification signal, or to output the ZQ flag signal based on the second master chip identification signal; The second AND gate, one input end connects the output end of the said second selector, another input end is used for receiving the background indication signal, the said background indication signal is used for representing the memory to work in the background mode; The first input selector is connected with the output end of the first AND gate, the second input end is connected with the output end of the second AND gate, the first selector is used for receiving the command indication signal or the background indication signal, the first output end is used for outputting a first internal calibration signal, and the first internal calibration signal is used for indicating the first main chip and the second main chip to calibrate; wherein the first input selector is configured to connect the first input to the first output based on the command indication signal or to connect the second input to the first output based on the background indication signal; The third signal receiver includes: And a fifth AND gate, one input end is used for receiving the ZQ mark signal, the other input end is used for receiving a first indication signal, the first indication signal is used for representing that the current chip is the first slave chip or the second slave chip, the output end is used for outputting a second internal calibration signal, and the second internal calibration signal is used for indicating that the first slave chip or the second slave chip is calibrated.
7. The memory device of claim 5 or 6, comprising: The first master chip and the second master chip further comprise the third signal receiver, and the slave chip further comprises the first signal receiver and/or the second signal receiver; the first master chip, the first slave chip, the second master chip, and the second slave chip further include: The system comprises a first input selector, a second input selector, a third input selector and a fifth input selector, wherein the first input selector is used for receiving the first internal calibration command, the sixth input selector is used for receiving the second internal calibration command, the third selector is used for receiving the first indication signal or the second indication signal, the second indication signal is used for representing that a current chip is the first main chip or the second main chip, the third output selector is used for outputting the first internal calibration command and the second internal calibration command, and the third input selector is configured to connect the sixth input to the third output end based on the first indication signal or connect the fifth input to the third output end based on the second indication signal.
8. The memory device of claim 1, wherein the first master chip, the first slave chip, the second master chip, and the second slave chip are packaged in a same memory device.
9. The memory device of claim 1, comprising: the first master chip and the first slave chip are packaged in different memory devices; the second master chip and the second slave chip are packaged in different memory devices; wherein the connection between the first and second transmission terminals encapsulated in different memory devices is provided by a wired or wireless interconnection between the memory devices.
10. The memory device of claim 1, comprising: The number of second slave chips = the number of first slave chips; The first master chip and the first slave chip are arranged based on a first array form of 1 column and N rows, and the first master chip is arranged at the position of the N rows; The second master chip and the second slave chip are arranged based on a second array form of 1 column and N rows, and the first master chip is arranged at the position of the N/2 th row; N-1 is the number of the first slave chips.
11. A ZQ calibration method applied to the memory device of any of claims 1-10, comprising: in a command mode, acquiring a ZQ calibration command externally applied to the memory device; in response to the ZQ calibration command, performing a first calibration operation on a first master chip; After the first calibration operation is finished, transmitting a ZQ mark signal to a first secondary chip of a first stage, and simultaneously executing a second calibration operation on the first primary chip; Performing the first calibration operation on the first stage first slave chip in response to the ZQ flag signal; after the first calibration operation of the first-stage first slave chip is finished, transmitting the ZQ mark signal to a next-stage first slave chip, and simultaneously executing the second calibration operation on the first-stage first slave chip until the first calibration operation of the last-stage first slave chip is finished; Completing the second calibration operation on the first slave chip of the last stage; Performing a first calibration operation on a second master chip in response to the delayed ZQ calibration command; after the first calibration operation is finished, transmitting a ZQ mark signal to a first-stage second slave chip, and simultaneously executing a second calibration operation on the second master chip; Performing the first calibration operation on the first stage second slave chip in response to the ZQ flag signal; after the first calibration operation of the first-stage second slave chip is finished, transmitting the ZQ mark signal to a next-stage second slave chip, and simultaneously executing the second calibration operation on the first-stage second slave chip until the last-stage second slave chip finishes the first calibration operation; And finishing the second calibration operation on the second slave chip of the last stage.
12. The ZQ calibration method of claim 11, comprising: the second calibration operation is completed for the first slave chip of the last stage, and the method also comprises the steps of transmitting the ZQ mark signal to the first master chip; The second calibration operation is completed for the second slave chip of the last stage, and the method further comprises the step of transmitting the ZQ mark signal to the second master chip.
13. The ZQ calibration method of claim 11, comprising: in a background mode, performing a first calibration operation on a first master chip in response to the ZQ calibration command; After the first calibration operation is finished, transmitting a ZQ mark signal to a first secondary chip of a first stage, and simultaneously executing a second calibration operation on the first primary chip; Performing the first calibration operation on the first stage first slave chip in response to the ZQ flag signal; after the first calibration operation of the first-stage first slave chip is finished, transmitting the ZQ mark signal to a next-stage first slave chip, and simultaneously executing the second calibration operation on the first-stage first slave chip until the first calibration operation of the last-stage first slave chip is finished; Transmitting the ZQ mark signal to a second master chip, and simultaneously executing a second calibration operation on the first slave chip of the last stage; performing the first calibration operation on the second master chip in response to the ZQ flag signal; after the first calibration operation is finished, transmitting a ZQ mark signal to a first-stage second slave chip, and simultaneously executing a second calibration operation on the second master chip; Performing the first calibration operation on the first stage second slave chip in response to the ZQ flag signal; after the first calibration operation of the first-stage second slave chip is finished, transmitting the ZQ mark signal to a next-stage second slave chip, and simultaneously executing the second calibration operation on the first-stage second slave chip until the last-stage second slave chip finishes the first calibration operation; And finishing the second calibration operation on the second slave chip of the last stage.
14. The ZQ calibration method according to claim 13, wherein in the background mode, the second calibration operation is completed for the last stage second slave chip while transmitting the ZQ flag signal to the first master chip.
15. The ZQ calibration method according to claim 11 or 13, wherein the first calibration operation is one of a pull-up calibration operation that generates a pull-up calibration code and a pull-down calibration operation that generates a pull-down calibration code, and the second calibration operation is the other of the pull-up calibration operation and the pull-down calibration operation.

Description

Memory device and ZQ calibration method Technical Field The present disclosure relates to the field of semiconductor circuit design, and more particularly, to a memory device and a ZQ calibration method. Background ZQ calibration is a very important function in a dynamic random access memory (Dynamic Random Access Memory, DRAM), and specifically relates to whether the output impedance of an output port is accurate or not, whether the termination resistance of an input port is accurate or not, and the deviation of these parameters can cause serious distortion caused by impedance mismatch in the signal transmission process, and the higher the signal frequency, the greater the influence of the distortion on the signal. The number of ZQ calibration resistors required by LPDDR5 has been specified in the packaging definition of JEDEC, for example, one ZQ calibration resistor is provided in DIS315 type chips and two ZQ calibration resistors are provided in POP496 type chips, so that the number of ZQ calibration resistors in LPDDR5 is obviously smaller than that in LPDDR 4. Along with the increasing demand for LPDDR capacity, more and more chips are put into one packaging body of the LPDDR, and each chip needs to be subjected to independent ZQ calibration due to individual difference, especially the packaging of the LPDDR5, the number of the ZQ calibration resistors is obviously reduced compared with the number of the ZQ calibration resistors in the LPDDR4, more chips need to share one ZQ, and how to realize the ZQ calibration by sharing the ZQ calibration resistors by multiple chips is a technical problem to be solved currently. Disclosure of Invention Embodiments of the present disclosure provide a memory device and a ZQ calibration method, by designing a new control circuit to achieve a theoretically infinite number of multi-chip shared ZQ calibration resistors. The embodiment of the disclosure provides a memory device, which comprises two calibration resistor interfaces, wherein the two calibration resistor interfaces are connected with the same ZQ calibration resistor; a first master chip, a plurality of cascaded first slave chips, a second master chip, and a plurality of cascaded second slave chips that are commonly connected to the ZQ calibration resistor; the first master chip, the first slave chip, the second master chip and the second slave chip are provided with a first transmission end and a second transmission end, and the first transmission end and the second transmission end are used for transmitting ZQ mark signals; the first master chip and the second master chip are used for transmitting ZQ mark signals through the second transmission end after calibration, the ZQ mark signals are represented by the first master chip and the second slave chip, the first slave chip and the second slave chip are used for transmitting the ZQ mark signals through the first transmission end after calibration is finished, the first slave chip and the second slave chip are used for transmitting the ZQ mark signals through the first transmission end and the second transmission end after calibration is finished, the first slave chip and the second slave chip are used for receiving ZQ calibration commands provided by a memory through the ZQ signal end in a command mode, and after the first slave chip and the second slave chip finish calibration, the ZQ mark signal is sent through the second transmission end until all the first slave chips or the second slave chips finish calibration. The method comprises the steps of configuring a plurality of chips calibrated through a first calibration interface into a first master chip and a plurality of first slave chips, configuring a plurality of chips calibrated through a second calibration interface into a second master chip and a plurality of second slave chips, wherein the first master chip performs ZQ calibration through a calibration resistor based on a ZQ calibration command provided by a memory, the second master chip performs ZQ calibration through a calibration resistor after delay based on a ZQ calibration command provided by the memory, and after the first master chip and the second master chip perform ZQ calibration through the calibration resistor, a ZQ mark signal is sent to the first slave chip and the second slave chip which are cascaded, and the first slave chip and the second slave chip which are cascaded perform ZQ calibration through the ZQ calibration resistor based on the ZQ mark signal in sequence, so that theoretically infinite multi-chip sharing ZQ calibration resistor performs ZQ calibration. In addition, the second transmission end of the first slave chip of the last stage is connected with the first transmission end of the first master chip, and the second transmission end of the second slave chip of the last stage is connected with the first transmission end of the second master chip. When the first master chip receives the ZQ mark signal, it proves that